Delay line calibration circuit comprising asynchronous arbiter element

A modulator device comprising:

• a pulse-width modulator;
• a delay line calibration circuit configured to control the delay of a delay line comprising delay elements such that the delay of the delay line in its perfectly calibrated state is equal to one clock period of a clock signal, wherein said delay line calibration circuit comprises
• an arbiter circuit comprising at least two inputs for receiving two signals, a unit configured to determine which of said two signals arrive first, and outputs, wherein a first of said at least two inputs is connected to an output of said delay line;
• a first D-Q flip-flop with a first input for receiving a first signal, a second input for receiving a clock signal and an output connected to an input of said delay line, for providing said first signal synchronized with a clock signal,
• a second D-Q flip-flop with an input connected to an output of said first D-Q flip-flop, a second input for receiving the clock signal and an output connected to a second input of said two inputs of said arbiter circuit, for providing a second signal synchronized with said clock signal, the second D-Q flip-flop generating a copy of the first signal synchronized with the clock signal exactly one clock cycle later, and
• a calibration circuit comprising inputs connected to the outputs of said arbiter circuit and configured to receive a signal from said arbiter circuit indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second D-Q flip-flop, said calibration circuit having an output connected to said delay line and configured to calibrate the delay of the delay line in accordance with the signal received from the arbiter circuit.

A delay line calibration circuit configured to control the delay of a delay line comprising delay elements such that the delay of the delay line in its perfectly calibrated state is equal to one clock period of a clock signal, wherein said delay line calibration circuit comprises:

• an arbiter circuit comprising at least two inputs for receiving two signals, a unit configured to determine which of said two signals arrive first, and outputs, wherein a first of said at least two inputs is connected to an output of said delay line;
• a first D-Q flip-flop with an input for receiving a first signal and an output connected to an input of said delay line, for providing said first signal synchronized with a clock signal,
• a second D-Q flip-flop with an input connected to an output of said first D-Q flip-flop, a second input for receiving the clock signal and an output connected to a second input of said two inputs of said arbiter circuit, for providing a second signal synchronized with said clock signal, the second D-Q flip-flop generating a copy of the first signal synchronized with the clock signal exactly one clock cycle later, and
• a calibration circuit comprising inputs connected to the outputs of said arbiter circuit and configured to receive a signal from said arbiter circuit indicative of whether the signal input to the arbiter circuit from the delay line is ahead or after the signal input to the arbiter circuit from the second D-Q flip-flop, said calibration circuit having an output connected to said delay line and configured to calibrate the delay of the delay line in accordance with the signal received from the arbiter circuit.