Semiconductor device and a method of manufacturing the same
AssigneeRenesas Electronics Corporation
InventorsMasami Koketsu, Toshiaki Sawada
Life of this patent
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Abstract
A technique for positioning a semiconductor chip and a mounting substrate with high precision using an alignment mark. In a semiconductor chip, a mark is formed in an alignment mark formation region over a semiconductor substrate in the same layer as an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. Pattern P1a is formed in the same layer as a second layer wiring, pattern P1b is formed in the same layer as a first layer wiring, pattern P2 is formed in the same layer as a gate electrode, and pattern P3 is formed in the same layer as an element isolation region.
Claims24
A semiconductor device comprising a semiconductor chip:
- the semiconductor chip including:
- an alignment mark formation region in which an alignment mark is formed, the alignment mark being used for positioning when mounting the semiconductor chip over a mounting substrate;
- and
- an integrated circuit formation region in which an integrated circuit is formed;
- the alignment mark having a mark region in which a mark is formed, and a background region surrounding the mark region;
- the integrated circuit formation region having a plurality of element isolation regions formed over a semiconductor substrate, a MISFET formed in an active region partitioned by the element isolation regions, and wirings formed over the semiconductor substrate and the MISFET;
- the wirings being formed across a plurality of layers;
- and
- the alignment mark being formed in the same layer as an uppermost wiring layer,
- wherein a first pattern is formed in the alignment mark formation region, the first pattern including a portion formed in a layer lower than the alignment mark,
- wherein one wiring layer is formed in a layer lower than the uppermost wiring layer in the integrated circuit formation region, and
- wherein the portion of the first pattern and the one wiring layer are formed in the same layer.
A semiconductor device comprising a semiconductor chip,
- the semiconductor chip including:
- an alignment mark formation region in which an alignment mark is formed, the alignment mark being used for positioning when mounting the semiconductor chip over a mounting substrate;
- and
- an integrated circuit formation region in which an integrated circuit is formed;
- the alignment mark having a mark region in which a mark is formed, and a background region surrounding the mark region;
- the integrated circuit formation region having a plurality of element isolation regions formed over a semiconductor substrate, a MISFET formed in an active region partitioned by the element isolation regions, and a wiring formed over the semiconductor substrate and the MISFET,
- wherein a first pattern is formed in the alignment mark formation region,
- wherein the first pattern includes a portion formed in a layer lower than the alignment mark, and
- wherein the wiring includes a portion formed in the same layer as the portion of the first pattern.
Dependencies are inferred from the claim text.