Apparatus and method for reducing pitch in an integrated circuit

An electronic chip package interconnect system comprising:

• a first and a second contact pad coupled to a substrate, the second contact pad positioned consecutive to the first contact pad;
• and
• a dielectric stack coupled to the substrate, the dielectric stack comprising:
• a first dielectric layer coupled to the substrate;
• a second dielectric layer coupled to the first dielectric layer such that a boundary is formed therebetween;
• a first cover pad positioned along the boundary and substantially aligned with the first contact pad, the first cover pad comprising a circular cover pad having an aperture formed therethrough;
• and
• a second cover pad positioned along a top surface of the second dielectric layer and substantially aligned with the second contact pad, the second cover pad comprising a circular cover pad having an aperture formed therethrough;
• wherein the dielectric stack has a second contact pad multi-layered via formed through the first and second dielectric layers extending from the second cover pad to the second contact pad;
• and
• wherein the dielectric stack further comprises a metal interconnect coupled to the second cover pad and extending down through the second contact pad multi-layered via to the second contact pad.

A method for minimizing contact pad pitch on an electronic chip package comprising:

• providing an electronic chip having a first and a second contact pad thereon, wherein the electronic chip is free of an intervening contact pad between the first and second contact pads;
• providing a first dielectric layer and a second dielectric layer each having a top surface and a bottom surface;
• adhering the bottom surface of the first dielectric layer to the electronic chip;
• forming a first contact pad via through the first dielectric layer at a location corresponding to the first contact pad;
• forming a first cover pad on one of the top surface of the first dielectric layer and the bottom surface of the second dielectric layer at a location corresponding to the first contact pad via;
• adhering the bottom surface of the second dielectric layer to the top surface of the first dielectric layer;
• forming a second contact pad via through the first and second dielectric layers at a location corresponding to the second contact pad, the second contact pad via comprising a multi-layered via;
• and
• forming a second cover pad on the top surface of the second dielectric layer at a location corresponding to the second contact pad via.