Structure and method to enhance both nFET and pFET performance using different kinds of stressed layers
AssigneeInternational Business Machines Corporation
InventorsBruce B. Doris, Haining Yang, Huilong Zhu
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Abstract
In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.
Claims3
A structure that adjusts carrier mobility in CMOS transistors comprising:
- a substrate,
- a first transistor having a gate dielectric, gate electrode, and source, drain, and gate regions, formed on said substrate,
- a second transistor having a gate dielectric, gate electrode, and source, drain, and gate regions, formed on said substrate,
- a first film providing tensile stress at least at the channel of said first transistor,
- a second film providing compressive stress at least at the channel of said second transistor, a portion of said second film extending in the same region of said substrate as a portion of said first film, and
- a shear force isolation layer separating said first film and said second film and said tensile and compressive stress therein in at least one area,
- wherein said first film is closer to the substrate than said second film, and does not fully surround said first transistor, but rather the sides only, while the remaining surfaces of said first transistor are contacted by said shear force isolation layer.
Dependencies are inferred from the claim text.