Transistor structure having a conductive layer formed contiguous in a single deposition
AssigneeHVVi Semiconductors, Inc.
InventorRobert Bruce Davies
Life of this patent
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Abstract
A semiconductor device is formed having a pedestal. The pedestal includes at least two dielectric layers. The pedestal has a sidewall and a major surface. A conductive layer is formed overlying the pedestal. A vertical portion of the conductive layer adjacent to the sidewall of the pedestal is a gate of the transistor. The portion of the conductive layer overlying the major surface can be used as interconnect. The gate and gate interconnect are contiguous and formed in a single process. A conductive shield layer may be integrated into the pedestal. The conductive shield layer functions as a faraday shield that reduces gate to drain capacitance of the device.
Claims28
A transistor comprising:
- a drain region of a first conductivity type;
- a pedestal comprising at least a first dielectric layer, a second dielectric layer, and a third dielectric layer wherein the pedestal overlies at least a portion of the drain region and wherein the pedestal has a sidewall surface and a first major surface;
- and
- a first conductive layer overlying the sidewall surface and the first major surface of the pedestal wherein a vertical portion of the first conductive layer adjacent to the sidewall surface of the pedestal comprises a gate of the transistor, wherein the first conductive layer is formed contiguous in a single deposition, and wherein a side wall of the first dielectric layer is etched to create an isotropic profile at a drain side of the gate.
A method of forming a transistor, the method comprising:
- forming a drain region of a first conductivity type;
- forming a pedestal overlying a portion of the drain region, the pedestal comprising a first dielectric layer, a second dielectric layer, a first conductive layer overlying the first and second dielectric layers, a third dielectric layer overlying the first conductive layer wherein the pedestal has a major surface and a sidewall;
- capping the sidewall of the pedestal with a fourth dielectric layer to cover an exposed portion of the conductive layer;
- and
- depositing a second conductive layer overlying the sidewall and major surface of the pedestal to respectively form a contiguous gate and gate interconnect in a single deposition.
A method of forming a transistor, comprising:
- forming a drain region of a first conductivity type;
- forming a pedestal overlying a portion of the drain region, the pedestal comprising at least a first dielectric layer and a second dielectric layer wherein the pedestal has a major surface and a sidewall;
- depositing a first conductive layer overlying the sidewall and the major surface of the pedestal;
- implanting dopant of a second conductivity type to form a tub region aligned to a vertical portion of the first conductive layer adjacent to the pedestal;
- and
- depositing a second conductive layer on the first conductive layer wherein the combined thickness of the first and second conductive layers is a gate length of the transistor.
A transistor comprising:
- a drain region of a first conductivity type;
- a pedestal comprising a first dielectric layer, a second dielectric layer, a first conductive layer overlying the first and second dielectric layers, a third dielectric layer overlying the first conductive layer, and a fourth dielectric layer overlying a sidewall of the pedestal wherein the pedestal overlies a portion of the drain region and where the pedestal includes a first major surface;
- and
- a second conductive layer overlying the sidewall surface and the first major surface of the pedestal wherein a vertical portion of the first conductive layer adjacent to the sidewall surface is a gate of the transistor and the second conductive layer is formed contiguous over the sidewall and major surface of the pedestal in a single deposition.
A transistor, comprising:
- a drain region of a first conductivity type;
- a pedestal comprising a stack of at least three horizontal dielectric layers and a stack of at least three or more vertical dielectric layers wherein the pedestal overlies a portion of the drain region and wherein the pedestal has a sidewall surface and a first major surface;
- a first conductive layer overlying the sidewall surface and the first major surface of the pedestal
- a tub region of a second conductivity type where a portion of the tub region underlies a vertical portion of the first conductive layer adjacent to the sidewall of the pedestal;
- and
- a source region of the first conductivity type formed in the tub region.
Dependencies are inferred from the claim text.