Transistor structure having dual shield layers
AssigneeHVVi Semiconductors, Inc.
InventorRobert Bruce Davies
Life of this patent
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Abstract
A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.
Claims7
A device, comprising:
- a transistor having a gate, a drain region, and a source region where the drain and the source region are of a first conductivity type;
- a trench in proximity to the drain region of the device where the trench has a sidewall and a major surface;
- a first dielectric layer overlying the sidewall and the major surface of the trench;
- and
- a first conductive layer overlying the sidewall of the trench where the first conductive layer does not overlie a majority of the major surface of the trench;
- a second dielectric layer overlying the first conductive layer;
- a second conductive layer overlying the second dielectric layer;
- wherein the first dielectric layer and the second dielectric layer comprise silicon dioxide;
- and further comprising a third dielectric layer overlying a portion of the first dielectric layer and underlying a portion of the first conductive layer, and a fourth dielectric layer overlying a portion of the second conductive layer and underlying a portion of the second dielectric layer.
Dependencies are inferred from the claim text.