Back to results
US 8,008,718 B2Granted
Semiconductor device and production method thereof
AssigneeSharp Kabushiki Kaisha
InventorSumio Katou
Life of this patent
Estimating the term…
Abstract
The semiconductor device of the present invention is a semiconductor device including P-type and N-type thin film transistors, at least one of the N-type thin film transistors having an off-set gate structure, at least one of the P-type thin film transistors having a LDD structure, wherein a P-type high concentration impurity layer for forming the at least one P-type thin film transistor is formed on the semiconductor layer in a region other than a region below a gate electrode and a sidewall spacer and contains a higher concentration of a P-type impurity together with an impurity contained in an N-type low concentration impurity layer and an N-type high concentration impurity layer for forming the N type thin film transistor.
Claims8
A semiconductor device comprising:
- a P-type thin film transistor having an LDD structure, an N-type thin film transistor having an off-set gate structure, and a substrate, the P-type thin film transistor including:
- a first semiconductor layer having a P-type low concentration impurity region;
- a first gate insulating film;
- and a first gate electrode on the substrate in this order, and further including:
- a first sidewall spacer formed on a side surface of the first gate electrode;
- and a P-type high concentration impurity layer having higher impurity concentration of a P-type impurity than that of the P-type low concentration impurity region;
- and the N-type thin film transistor including:
- a second semiconductor layer;
- a second gate insulating film;
- and a second gate electrode on the substrate in this order, and further including:
- a second sidewall spacer formed on a side surface of the second gate electrode;
- an N-type low concentration impurity layer;
- and an N-type high concentration impurity layer having higher impurity concentration of an N-type impurity than that of the N-type low concentration impurity layer;
- wherein the N-type low concentration impurity layer and the N-type high concentration impurity layer are stacked on the second semiconductor layer in a region other than a region below the second gate electrode and the second sidewall spacer, the P-type low concentration impurity region is formed in a region other than a region below the first gate electrode, the P-type high concentration impurity layer is formed on the P-type low concentration impurity region of the first semiconductor layer in a region other than a region below the first gate electrode and the first sidewall spacer, the P-type high concentration impurity layer contains the P-type impurity together with the N-type impurity contained in the N-type low concentration impurity layer and the N-type high concentration impurity layer, and a sum of a thickness of the N-type low concentration impurity layer and a thickness of the N-type high concentration impurity layer is substantially equal to a thickness of the P-type high concentration impurity layer.
11 more elements
A semiconductor device comprising:
- a P-type thin film transistor having an off-set gate structure, and an N-type thin film transistor having an LDD structure, and a substrate, the N-type thin film transistor including:
- a first semiconductor layer having an N-type low concentration impurity region;
- a first gate insulating film;
- and a first gate electrode on the substrate in this order, and further including:
- a first sidewall spacer formed on a side surface of the first gate electrode;
- and an N-type high concentration impurity layer having higher impurity concentration of an N-type impurity than that of the N-type low concentration impurity region;
- and the P-type thin film transistor including:
- a second semiconductor layer;
- a second gate insulating film;
- and a second gate electrode on the substrate in this order, and further including:
- a second sidewall spacer formed on a side surface of the second gate electrode;
- a P-type low concentration impurity layer;
- and a P-type high concentration impurity layer having higher impurity concentration of a P- type impurity than that of the P-type low concentration impurity layer;
- wherein the P-type low concentration impurity layer and the P-type high concentration impurity layer are stacked on the second semiconductor layer in a region other than a region below the second gate electrode and the second sidewall spacer, the N-type low concentration impurity region is formed in a region other than a region below the first gate electrode, the N-type high concentration impurity layer is formed on the N-type low concentration impurity region of the first semiconductor layer in a region other than a region below the first gate electrode and the first sidewall spacer, the N-type high concentration impurity layer contains the N-type impurity together with the P-type impurity contained in the P-type low concentration impurity layer and the P-type high concentration impurity layer, and a sum of a thickness of the P-type low concentration impurity layer and a thickness of the P-type high concentration impurity layer is substantially equal to a thickness of the N-type high concentration impurity layer.
11 more elements
Dependencies are inferred from the claim text.