Vertical SOI trench SONOS cell
AssigneeInternational Business Machines Corporation
InventorsDavid M. Dobuzinsky, Herbert L. Ho, Jack A. Mandelman, Yoichi Otani
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is created in a semiconductor-on-insulator (SOI) substrate is provided that allows for the integration of dense non-volatile random access memory (NVRAM) cells in SOI-based complementary metal oxide semiconductor (CMOS) technology. The trench is processed using conventional trench processing and it is processed near the beginning of the inventive method that allows for the fabrication of the memory cell to be fully separated from SOI logic processing.
Claims11
A semiconductor structure comprising:
- a semiconductor-on-insulator substrate comprising a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer;
- and
- at least one vertical trench SONOS memory cell located within said semiconductor-on-insulator substrate, said at least one vertical trench SONOS memory cell includes a source diffusion located beneath said vertical trench, a select gate channel located on one side of said vertical trench, an outdiffused/Si-containing bridge located above and in contact with said select gate channel, and a silicided doped region located adjacent to and in contact with an upper portion of said bridge, wherein said bridge is present within said top semiconductor layer, said buried insulating layer and said lower semiconductor layer.
A semiconductor structure comprising
- a semiconductor-on-insulator substrate comprising a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer;
- at least one pair of vertical trench SONOS memory cells located within said semiconductor-on-insulator substrate, each vertical trench SONOS memory cell includes a source diffusion located beneath said vertical trench, a select gate channel located on one side of said vertical trench, an outdifussed/Si-containing bridge located above and in contact with said select gate channel, and a silicided doped region located adjacent to and in contact with an upper portion of said bridge, wherein said bridge is present within said top semiconductor layer, said buried insulating layer and said lower semiconductor layer;
- and
- a deep trench isolation region separating each pair of memory cells.
Dependencies are inferred from the claim text.