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US 8,008,702 B2Granted
Multi-transistor non-volatile memory element
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih Wei Wang, Chun Jung Lin
Life of this patent
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Abstract
A multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.
Claims6
A system comprising:
- a substrate;
- a first active region and a second active region disposed in the substrate;
- a first and second multi-transistor element disposed on the substrate, the first and second multi-transistor elements each including:
- an isolation feature;
- a floating gate stack adjacent to the isolation feature, the floating gate stack including a first region, a second region, and a notch interposing the first and second regions;
- a control gate stack adjacent to the floating gate stack;
- a first bitline coupled to the first region of the floating gate stack;
- a second bitline coupled to the second region of the floating gate stack;
- and
- a wordline adjacent to the floating gate stack and the control gate stack;
- an erase gate disposed on the substrate and coupled to the first and second multi-transistor elements;
- and
- a common source coupled to the first and second multi-transistor elements,
- wherein the first multi-transistor element is coupled to the first active region and the second multi-transistor element is coupled to the second active region, and
- wherein the first and second multi-transistor elements are disposed such that the notch of their respective floating gate stacks open in opposite directions.
12 more elements
Dependencies are inferred from the claim text.