Semiconductor memory devices having vertical channel transistors and related methods

A semiconductor memory device comprising:

• a semiconductor substrate including a plurality of active regions, wherein each of the active regions extends in a first direction parallel with respect to a surface of the semiconductor substrate;
• a plurality of pillars extending from respective active regions in a direction perpendicular with respect to the surface of the semiconductor substrate with each of the pillars including a respective channel region on a sidewall thereof;
• a plurality of gate insulating layers surrounding respective sidewalls of the plurality of pillars;
• a plurality of word lines extending in a second direction parallel with respect to the surface of the semiconductor substrate wherein the first and second directions are different and wherein respective ones of the word lines surround sidewalls of respective ones of the plurality of pillars so that the gate insulating layers are between the word lines and the pillars;
• a plurality of contact plugs electrically connected to respective ones of the active regions and spaced apart from the word lines;
• and
• a plurality of bit lines electrically connected to respective ones of the active regions through respective ones of the contact plugs wherein the plurality of bit lines extend in the first direction;
• wherein each of the plurality of contact plugs includes a recess in a surface thereof opposite the substrate, wherein each of the bit lines includes a lower surface adjacent the semiconductor substrate and sidewalls substantially perpendicular with respect to the surface of the substrate, and wherein portions of the lower surface and at least one of the sidewalls of one of the bit lines is in direct contact with one of the contact plugs at the recess thereof.

A semiconductor memory device comprising:

• a semiconductor substrate including an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate;
• a first pillar extending from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate wherein the first pillar includes a first channel region on a sidewall thereof;
• a first gate insulating layer surrounding a sidewall of the first pillar;
• a first word line extending in a second direction parallel with respect to the surface of the semiconductor substrate wherein the first and second directions are different and wherein the first word line surrounds the sidewall of the first pillar so that the first gate insulating layer is between the first word line and the first pillar;
• a second pillar extending from the active region in the direction perpendicular with respect to the surface of the semiconductor substrate wherein the second pillar includes a second channel region on a sidewall thereof;
• a second gate insulating layer surrounding the sidewall of the second pillar;
• and
• a second word line extending in the second direction wherein the second word line surrounds the sidewall of the second pillar so that the second gate insulating layer is between the second word line and the second pillar,
• a contact plug electrically connected to the impurity region and spaced apart from the first and second word lines;
• and
• a bit line electrically connected to the impurity region through the contact plug wherein the bit line extends in the first direction.