US 8,008,689 B2 · MIS gate structure type HEMT device and method of fabricating MIS gate structure type HEMT device

Abstract

A normally-off operation type HEMT device excellent in characteristics can be realized. A two-dimensional electron gas region is formed in a periphery of a hetero-junction interface of a base layer and a barrier layer, so that access resistance in an access portion, that is, between a drain and a gate and between a gate and a source is sufficiently lowered, and at the same time, a P-type region is formed immediately under the gate. This realizes a normally-off type HEMT device having a low on-resistance. Further, when a film thickness of an insulating layer is defined as t (nm) and a relative permittivity of a substance forming the insulating layer is defined as k, a threshold voltage as high as +3 V or more can be attained by satisfying k/t≦0.85 (nm−1).

Claims17

Dependent claims

A MIS gate structure type HEMT device comprising:

(a) a semiconductor layer including:
(a-1) a base layer made of a first Group III nitride and having conductivity of N-type and a specific resistance of 1×107 Ωcm or more, or having conductivity of P-type;
(a-2) a barrier layer made of a second Group III nitride having a wider band gap than said first Group III nitride;
and
(a-3) a P-type region having conductivity of P type;
(b) a source electrode and a drain electrode, formed on said barrier layer;
(c) a gate electrode;
and
(d) an insulating layer located between said gate electrode and said semiconductor layer, wherein
said barrier layer is formed adjacent to said base layer and said insulating layer,
said base layer has a two-dimensional electron gas region in a periphery of an interface with said barrier layer, and
said P-type region is formed immediately under said insulating layer and penetrates said barrier layer and said two-dimensional electron gas region in a range substantially concealed in said gate electrode when said gate electrode is observed in plane view from a surface side.

9 more elements

A method of fabricating a MIS gate structure type HEMT device including an insulating layer between a gate electrode and a semiconductor layer, said method comprising the following steps:

(a) forming a two-dimensional electron gas region of a base layer in a periphery of an interface with a barrier layer, said step (a) comprising the following steps:
(a-1) forming said base layer having conductivity of N-type and a specific resistance of 1×107 Ωcm or more or conductivity of P-type by doping a first Group III nitride with a prescribed dopant;
(a-2) forming said barrier layer using a second Group III nitride having a wider band gap than said first Group III nitride;
and
(b) forming a P-type region having a main P-type region and an auxiliary P-type region in a range substantially concealed in said gate electrode when said gate electrode is observed in plane view from a surface side,
said auxiliary P-type region being a diffusion region of Mg contained in said main P-type region, said step (b) comprising the following steps:
(b-1) removing a portion of said barrier layer and said base layer and thereafter forming said main P-type region made of GaN with doping Mg in a manner that a removed portion is embedded and a top face of an embedded portion is approximately continuous with a top face of said barrier layer;
and
(b-2) carrying out activation treatment for activating Mg doped in said main P-type region;
(c) forming said insulating layer on a top face of said semiconductor layer;
and
(d) forming a source electrode and a drain electrode at prescribed positions of the top face of said barrier layer and forming a gate electrode at a prescribed position of a top face of said insulating layer.

9 more elements

A MIS gate structure type HEMT device including an insulating layer between a gate electrode and a semiconductor layer, said HEMT device fabricated by the following steps:

(a) forming a two-dimensional electron gas region of a base layer in a periphery of an interface with a barrier layer, said step (a) comprising the following steps:
(a-1) forming said base layer having conductivity of N-type and a specific resistance of 1×107 Ωcm or more or conductivity of P-type by doping a first Group III nitride with a prescribed dopant;
and
(a-2) forming said barrier layer using a second Group III nitride having a wider band gap than said first Group III nitride;
and
(b) forming a P-type region having a main P-type region and an auxiliary P-type region in a range substantially concealed in said gate electrode when said gate electrode is observed in plane view from a surface side,
said auxiliary P-type region being a diffusion region of Mg contained in said main P-type region, and comprising the following steps:
(b-1) removing a portion of said barrier layer and said base layer and thereafter forming said main P-type region made of GaN with doping Mg in a manner that a removed portion is embedded and a top face of an embedded portion is approximately continuous with a top face of said barrier layer;
and
(b-2) carrying out activation treatment for activating Mg doped in said main P-type region;
(c) forming said insulating layer on a top face of said semiconductor layer;
and
(d) forming a source electrode and a drain electrode at prescribed positions of the top face of said barrier layer and forming a gate electrode at a prescribed position of a top face of said insulating layer.

10 more elements

Dependencies are inferred from the claim text.

MIS gate structure type HEMT device and method of fabricating MIS gate structure type HEMT device

Life of this patent

MIS gate structure type HEMT device and method of fabricating MIS gate structure type HEMT device

Life of this patent

Abstract

Claims17