Method for reducing dielectric overetch using a dielectric etch stop at a planar surface
AssigneeSanDisk 3D LLC
InventorsSamuel V. Dunton, Christopher J. Petti, Usha Raghuram
Life of this patent
Estimating the term…
Loading patent…
AssigneeSanDisk 3D LLC
InventorsSamuel V. Dunton, Christopher J. Petti, Usha Raghuram
Estimating the term…
A substantially planar surface coexposes conductive or semiconductor features and a dielectric etch stop material. A second dielectric material, different from the dielectric etch stop material, is deposited on the substantially planar surface. A selective etch etches a hole or trench in the second dielectric material, so that the etch stops on the conductive or semiconductor feature and the dielectric etch stop material. In a preferred embodiment the substantially planar surface is formed by filling gaps between the conductive or semiconductor features with a first dielectric such as oxide, recessing the oxide, filling with a second dielectric such as nitride, then planarizing to coexpose the nitride and the conductive or semiconductor features.
A method for reducing dielectric overetch, the method comprising:
A method for forming first conductors above first pillars, the method comprising:
A method for minimizing dielectric overetch in a monolithic three dimensional memory array, the method comprising:
Dependencies are inferred from the claim text.