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AssigneeHynix Semiconductor Inc.
InventorHae Chan Park
Estimating the term…
A phase change memory device having an increased sensing margin for improved cell efficiency. The phase change memory device includes a plurality of diodes formed in an active region of a semiconductor substrate; an insulation layer pattern formed on the respective diodes; a phase change layer formed on the insulation layer pattern in such a way as not to be electrically connected with the diodes; bit lines formed over the phase change layer; and a global X-decoder line formed over the bit lines. The present invention suppresses current flow in a phase change memory device because the dummy cell string and the dummy active region are not electrically connected with each other under the global X-decoder line, whereby preventing parasitic current from being produced in the phase change memory device.
A method for manufacturing a phase change memory device, comprising the steps of:
Dependencies are inferred from the claim text.
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Electrodes: adapted for resistive heating
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: comprising selection components having two electrodes, e.g. diodes
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: arrangements comprising multiple bistable or multi-stable switching…
Manufacture or treatment of multistable switching devices: shaping switching materials
About 3 years of term left · ends 6 Nov 2029 (estimated)
The present application claims priority to Korean patent application number 10-2008-0116373 filed on Nov. 21, 2008, which is incorporated herein by reference in its entirety.
The present invention relates generally to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device having an increased sensing margin and improved cell efficiency and a method for manufacturing the same.
In general, when configuring the memory cells of a phase change memory device, cell arrays are constructed by repeatedly locating memory cell strings, wherein each of these memory cell strings includes a plurality of diodes that include an epi-silicon layer. That is, in one cell array, 8-bit memory cell strings are located in a word line direction, and 8-bit memory cell strings as well as a global X-decoder line that is connected to a global X-decoder can be located in a bit line direction.
FIG. 1 is a cross-sectional view illustrating a phase change memory device in accordance with an embodiment of the present invention.
FIGS. 2A through 2J are plan views illustrating the processes of a method for manufacturing a phase change memory device in accordance with another embodiment of the present invention.
FIGS. 3A through 3J are cross-sectional views taken along the lines X-X′ of FIGS. 2A through 2J, illustrating the processes of the method for manufacturing a phase change memory device in accordance with another embodiment of the present invention.
Hereafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a sectional view illustrating a phase change memory device in accordance with an embodiment of the present invention.
Referring to FIG. 1, an isolation structure 102 is formed in a semiconductor substrate 100 to delimit an active region, and an N-type impurity region 104 is formed in the surface of the active region. A ground voltage is applied to the active region that is formed with the N-type impurity region 104. A first interlayer dielectric 106 is formed in the active region, and a plurality of diodes 108 are formed in the first interlayer dielectric 106 to be placed in the active region. The diodes 108 comprise vertical PN diodes, wherein each of the PN diodes includes an N region N and a P region P. Also, each of the PN diodes are sequentially stacked on the N-type impurity region 104. An ohmic contact layer 110 is formed on the respective diodes 108. The ohmic contact layer 110 includes, for example, a metal silicide layer. Lower contact plugs 112 are formed in the first interlayer dielectric 106.