Methods of fabricating flash memory devices including substantially uniform tunnel oxide layers
AssigneeSamsung Electronics Co., Ltd.
InventorJae-Hoon Kim
Life of this patent
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Abstract
A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending through the first conductive layer and the first insulating layer to define an active region in the memory cell region between the trench isolation regions, and selectively removing the first conductive layer and the first insulating layer from the memory cell region of the substrate to expose a surface of the active region between the trench isolation regions.
Claims16
A method of forming a flash memory device in a substrate including a memory cell region and a peripheral circuit region, the method comprising:
- forming a first gate oxide layer on the substrate;
- forming a first gate layer comprising polycrystalline silicon on the first gate oxide layer:
- forming trench isolation regions in the substrate extending through the first gate oxide layer and the first gate layer to define first active regions of the memory cell region and second active regions of the peripheral circuit region;
- and
- selectively removing the first gate oxide layer and the first gate layer from the first active regions in the memory cell region while maintaining the first gate layer and the first gate oxide layer in the second active regions in the peripheral circuit region.
A method of forming a flash memory device in a substrate including a memory cell region and a peripheral circuit region, the method comprising:
- forming a first gate oxide layer on the substrate;
- forming a first gate layer comprising polycrystalline silicon on the first gate oxide layer:
- forming trench isolation regions in the substrate extending through the first gate oxide layer and the first gate layer to define first active regions of the memory cell region and second active regions of the peripheral circuit region;
- forming a masking layer over the first gate layer and the first gate oxide layer in the peripheral circuit region;
- selectively removing the first gate oxide layer and the first gate layer from the first active regions in the memory cell region, wherein selectively removing the first gate oxide layer and the first gate layer from the memory cell region comprises selectively etching the first gate oxide layer and the first gate layer in the memory cell region while maintaining the first gate layer and the first gate oxide layer in the peripheral circuit region;
- forming second gate oxide layers respectively on each of the first active regions;
- forming floating gate layers respectively on each of the second gate oxide layers;
- forming a third gate oxide layer on the floating gate layers;
- and
- forming a control gate on the third gate oxide layer.
Dependencies are inferred from the claim text.