Non-volatile semiconductor memory device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorTakuji Kuniya
Life of this patent
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Abstract
A non-volatile semiconductor memory device comprises a plurality of memory cells, each including a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a floating gate formed on the semiconductor substrate with the inclusion of the first insulating film, a second insulating film formed on the floating gate, and a control gate formed on the floating gate with the inclusion of the second insulating film; an element isolation insulating film formed in the semiconductor substrate and extending in a gate-length direction to isolate between memory cells adjoining in a gate-width direction; and an air gap formed on the element isolation insulating film and between floating gates adjoining in the gate-width direction.
Claims10
A method of manufacturing a non-volatile semiconductor memory device, comprising:
- forming a first insulating film on a semiconductor substrate;
- forming on said first insulating film a first electrode layer to be turned into a floating gate;
- forming an element isolation trench extending from said first electrode layer into said semiconductor substrate to define an element forming region in said semiconductor substrate;
- forming a first buried film and a second buried film sequentially in said element isolation trench in said semiconductor substrate;
- forming a second insulating film on said first electrode layer and said second buried film;
- forming on said second insulating film a second electrode layer to be turned into a control gate;
- selectively removing said second electrode layer to form said control gate crossing said element forming region and said element isolation trench;
- selectively removing said second insulating film in a region not covered with said control gate;
- removing said second buried film after selectively removing said second insulating film;
- and
- selectively removing said first electrode layer in a region not covered with said control gate to form said floating gate.
Dependencies are inferred from the claim text.