Method to form a semiconductor device having gate dielectric layers of varying thicknesses

A method for fabricating an integrated circuit device, the method comprising:

• providing a substrate having a first region, a second region, and a third region;
• forming a first gate structure in the first region, a second gate structure in the second region, and a third gate structure in the third region, wherein the first, second, and third gate structures include a gate dielectric layer, the gate dielectric layer being a first thickness in the first gate structure, a second thickness in the second gate structure, and a third thickness in the third gate structure;
• and
• wherein forming the gate dielectric layer of the first, second, and third thicknesses includes:
• while forming the first, second, and third gate structures, forming an etching barrier layer over the gate dielectric layer in at least one of the first, second, or third regions;
• and
• prior to forming the gate dielectric layer in at least one of the first, second, or third regions, performing an implantation process on the at least one of the first, second, or third regions.

A method for fabricating an integrated circuit device having gate dielectric layers of varying thicknesses, the method comprising:

• providing a substrate with a first region, a second region, and a third region;
• forming a first gate dielectric layer having a first thickness in the first region;
• forming a barrier layer over the first gate dielectric layer;
• forming a dummy gate dielectric layer in the second and third regions;
• forming a dummy gate layer over the barrier layer and the dummy gate dielectric layer;
• performing a gate patterning process to form gate structures in the first, second, and third regions;
• removing the dummy gate layer from the gate structures in the first, second, and third regions, thereby forming openings in the gate structures in the first, second, and third regions;
• performing an implantation process in the second or third region;
• removing the dummy gate dielectric layer from the openings of the gate structures in the second and third regions;
• forming an interfacial layer to partially fill in the openings of the gate structures in the second and third regions, wherein the interfacial layer in the second region exhibits a second thickness and the interfacial layer in the third region exhibits a third thickness.