Method for fabricating 1T-DRAM on bulk silicon

A method for fabricating a one transistor dynamic random access memory cell on bulk silicon, the method comprising:

• forming an integrated circuit in the bulk silicon, wherein the integrated circuit includes a first contact and a second contact;
• depositing a first inter-layer dielectric over an upper surface of the integrated circuit;
• depositing a layer of amorphous silicon on the first inter-layer dielectric;
• removing portions of the amorphous silicon deposited on the first inter-layer dielectric over each of the first contact and the second contact such that a remainder portion of the amorphous silicon remains on the first inter-layer dielectric in between the first contact and the second contact;
• depositing a gate oxide on the remainder portion of the amorphous silicon;
• depositing a polysilicon layer on the gate oxide;
• patterning the gate oxide and the polysilicon layer to form (i) a first gate and (ii) a second gate, wherein the first gate is laterally adjacent to the second gate;
• implanting ions into the amorphous silicon at locations adjacent to each of the first gate and the second gate, wherein the ions implanted in between the first gate and the second gate form a source region that is shared by the first gate and the second gate, and wherein the ions not implanted in between the first gate and the second gate respectively form a first drain region and second drain region for the first gate and the second gate;
• depositing a second inter-layer dielectric over each of (i) the first gate, (ii) the second gate, (iii) the first drain region of the first gate, (iv) the second drain region of the second gate, (v) the source region shared by the first gate and the second gate, (vi) the first contact of the integrated circuit, and (vii) the second contact of the integrated circuit;
• removing portions of the second inter-layer dielectric deposited over each of the first contact of the integrated circuit, the second contact of the integrated circuit, and the source region shared by the first gate and the second gate;
• forming a third contact, a fourth contact, and a fifth contact within the second inter-layer dielectric respectively over each of the first contact of the integrated circuit, the second contact of the integrated circuit, and the source region shared by the first gate and the second gate;
• and
• depositing a metal bit line over the third contact, the fourth contact, the fifth contact, and the second inter-layer dielectric.