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US 8,008,136 B2Granted
Fully silicided gate structure for FinFET devices
AssigneeAdvanced Micro Devices, Inc.
InventorsMing-Ren Lin, Witold P. Maszara, Haihong Wang, Bin Yu
Life of this patent
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Abstract
A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.
Claims12
A method of manufacturing a semiconductor device, comprising:
- forming source and drain regions in a first silicon layer of the semiconductor device;
- forming a fin structure, the fin structure including first and second side surfaces;
- forming a first dielectric layer on the first and second side surfaces of the fin structure;
- forming a protective layer on a top surface of the fin structure;
- depositing a second silicon layer over the fin structure;
- etching the second silicon layer to form at least one gate electrode;
- performing a first silicide process to convert a portion of the first and second silicon layers into a metal-silicide compound that ranges in thickness from 50 Å to 700 Å;
- and
- depositing, after performing the first silicide process, a second dielectric layer over the device;
- planarizing the second dielectric layer to expose the metal-silicide compound of the gate electrode, without exposing the source and drain regions;
- performing a second silicide process to convert a remaining portion of the second silicon layer into the metal-silicide compound to form a fully-silicided gate electrode,
- where performing the second silicide process includes depositing a metal layer over the metal-silicide compound, of the gate electrode, that results from performing the first silicide process,
- where the protective layer protects the fin structure from the second silicide process,
- where the second silicide process is separate from the first silicide process, and
- where the fully-silicided gate electrode causes stress on the fin structure to enhance mobility in the fin structure.
12 more elements
A method comprising:
- etching a first silicon layer to form source and drain regions;
- forming a fin structure, the fin structure including first and second side surfaces;
- depositing a second silicon layer over the fin structure;
- etching the second silicon layer to form at least one gate electrode;
- depositing a first metal layer on a top surface of the at least one gate electrode and the source and drain regions;
- performing a first silicide process to convert a portion of the first and second silicon layers into a metal-silicide compound that ranges in thickness from 50 Å to 700 Å;
- depositing, after performing the first silicide process, a dielectric layer over the gate electrode and the source and drain regions;
- planarizing the dielectric layer to expose the metal-silicide compound of the gate electrode, without exposing the source and drain regions;
- depositing a second metal layer on a top surface of the metal-silicide compound of the gate electrode;
- and
- performing a second silicide process after depositing the second metal layer to convert a remaining portion of the second silicon layer into the metal-silicide compound to form a fully-silicided gate electrode, where the fully-silicided gate electrode causes stress on the fin structure to enhance mobility in the fin structure.
8 more elements
A method comprising:
- forming a gate electrode over a fin structure;
- forming source and drain regions at opposite ends of the fin structure;
- depositing a first metal layer on a top surface of the gate electrode;
- performing a first silicide process to convert a portion of the gate electrode, the source region, and the drain region into a metal-silicide compound;
- depositing, after performing the first silicide process, a dielectric layer over the gate electrode, the source region, and the drain region;
- planarizing the delectric layer to expose the metal-silicide compound of the gate electrode, without exposing the source and drain regions;
- depositing a second metal layer on a top surface of the metal-silicide compound of the gate electrode;
- and
- performing a second silicide process after depositing a second metal layer to form a fully-silicided gate electrode, where the fully-silicided gate electrode causes stress on the fin structure to enhance mobility.
6 more elements
Dependencies are inferred from the claim text.