System and method for stacked die embedded chip build-up

A method of forming an embedded chip package comprising:

• providing an initial polymer laminate layer and a first chip secured thereto, the first chip having chip pads thereon;
• patterning the initial polymer laminate layer to include a plurality of vias and a plurality of metal interconnects, such that a portion of the plurality of metal interconnects extend down through respective vias and are metalized directly to the chip pads on the first chip;
• providing an additional chip;
• providing a plurality of additional polymer laminate layers, wherein a portion of the plurality of additional polymer laminate layers includes a chip opening formed therein for placement of one of the first chip and the additional chip;
• selectively coupling the additional chip and each of the plurality of additional polymer laminate layers to the initial polymer laminate layer;
• after the coupling of each of the plurality of additional polymer laminate layers, selectively patterning the additional polymer laminate layer to include a plurality of vias and a plurality of metal interconnects such that each of the plurality of metal interconnects extends through a respective via and is directly metalized to one of a metal interconnect on a neighboring polymer laminate layer and a chip pad on the additional chip;
• and
• electrically coupling a plurality of input/output (I/O) connections to the metal interconnects on an outermost polymer laminate layer of the plurality of additional polymer laminate layers, wherein the I/O connections are electrically connected to the first chip and to the additional chip by way of the plurality of metal interconnects.

A method for manufacturing a wafer level package comprising:

• providing a plurality of chips, each of the plurality of chips having chip pads formed thereon;
• providing a plurality of polymer laminate layers, wherein each of a portion of the plurality of polymer laminate layers includes a chip opening formed therein for placement of one of the plurality of chips therein;
• and
• assembling a wafer level package using the plurality of chips and the plurality of polymer laminate layers, wherein assembling the wafer level package comprises:
• applying a first chip to an initial polymer laminate layer;
• patterning the initial polymer laminate layer to include a plurality of vias and a plurality of metal interconnects, each of the plurality of metal interconnects extending down through a respective via to electrically couple the initial polymer laminate layer to the first chip;
• selectively applying, in a stacked arrangement, additional polymer laminate layers and additional chips to the initial polymer laminate layer and the first chip;
• and
• upon application of each additional polymer laminate layer, patterning the additional polymer laminate layer to form a plurality of vias and a plurality of metal interconnects extending down through the vias, such that the metal interconnects in each of the additional polymer laminate layers electrically couples that polymer laminate layer to a previously applied additional polymer laminate layer or a previously applied additional chip.