US 8,008,107 B2Granted

Semiconductor wafer pre-process annealing and gettering method and system for solar cell formation

AssigneeCalisolar, Inc.

InventorsFritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke

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Abstract

Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered. Multicrystalline semiconductor wafers having grain boundaries with impurities may also undergo the annealing and gettering of dispersed defects to the grain boundaries, further increasing the semiconductor substrate purity levels.

Claims19

Dependent claims

A method for pre-processing a semiconductor wafer made of low grade silicon having a thickness of approximately 150 μm or less, and having generally dispersed defects, said semiconductor wafer comprising top and bottom near-surface layers, each near-surface layer containing enhanced amounts of lattice defects predisposed to receive and hold dispersed defects and related clusters and a bulk region with dispersed defects throughout said bulk region, the method comprising:

preserving said lattice defects caused by mechanical damage occurring at said near-surface layers for permitting use of near-surface layers as a gettering site for said dispersed defects;
forming said at least one surface contaminant layer in the course of wire sawing to comprise metal atoms from the group consisting essentially of Cu, Ni, Fe in the concentration range 1010-1017 metal atoms/cm2;
and
collecting said dispersed defects at said lattice defects in said near-surface layers by performing the steps of:
annealing said semiconductor wafer to a temperature sufficient for gettering said dispersed defects to said lattice defects and related clusters within the near-surface layers;
cooling said semiconductor wafer following said annealing step for retaining said defects as clusters predominantly within said near-surface layers, thereby increasing the impurity level of said semiconductor wafer predominantly in said near-surface layers and changing the distribution of said dispersed defects to a depth-dependent distribution within said wafers;
and
removing said near-surface layers including said impurity clusters for yielding a generally higher purity level denuded zone substantially across a remaining thickness of said semiconductor wafer.

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Dependencies are inferred from the claim text.