US 8,004,042 B2Granted

Static random access memory (SRAM) cell and method for forming same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsLie-Yong Yang, Feng-Ming Chang, Chang-Ta Yang, Ping-Wei Wang

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Abstract

In accordance with an embodiment of the present invention, a static random access memory (SRAM) cell comprises a first pull-down transistor, a first pull-up transistor, a first pass-gate transistor, a second pull-down transistor, a second pull-up transistor, a second pass-gate transistor, a first linear intra-cell connection, and a second linear intra-cell connection. Active areas of the transistors are disposed in a substrate, and longitudinal axes of the active areas of the transistors are all parallel. The first linear intra-cell connection electrically couples the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor. The second linear intra-cell connection electrically couples the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor.

Claims17

Dependent claims

A static random access memory (SRAM) cell comprising:

a first pull-down transistor;
a first pull-up transistor;
a first pass-gate transistor;
a second pull-down transistor;
a second pull-up transistor;
a second pass-gate transistor, wherein active areas of the transistors are disposed in a substrate, and wherein longitudinal axes of the active areas of the transistors are all parallel;
a first linear intra-cell connection electrically coupling the active area of the first pull-down transistor, the active area of the first pull-up transistor, and the active area of the first pass-gate transistor to a gate electrode of the second pull-down transistor and a gate electrode of the second pull-up transistor, wherein all outer edges of a first top surface of the first linear intra-cell connection form one first rectangle of the first top surface, the first top surface being parallel to a substrate top surface, wherein a longitudinal axis of the first top surface aligns with the gate electrode of the second pull-down transistor and the gate electrode of the second pull-up transistor;
and
a second linear intra-cell connection electrically coupling the active area of the second pull-down transistor, the active area of the second pull-up transistor, and the active area of the second pass-gate transistor to a gate electrode of the first pull-down transistor and a gate electrode of the first pull-up transistor, wherein all outer edges of a second top surface of the second linear intra-cell connection form one second rectangle of the second top surface, the second top surface being parallel with the substrate top surface, wherein a longitudinal axis of the second top surface aligns with the gate electrode of the first pull-down transistor and the gate electrode of the first pull-up transistor.

6 more elements

A static random access memory (SRAM) cell comprising:

a plurality of transistors having active areas arranged in parallel in a semiconductor substrate, wherein the plurality of transistors comprise a first pass-gate transistor, a first pull-down transistor, a first pull-up transistor, a second pull-up transistor, a second pull-down transistor, and a second pass-gate transistor;
a first intra-cell connection on the semiconductor substrate electrically coupling an active area of the first pass-gate transistor, an active area of the first pull-down transistor, and an active area of the first pull-up transistor to a gate of the second pull-up transistor and a gate of the second pull-down transistor, wherein the first intra-cell connection has a first cross-sectional area parallel to a top surface of the substrate, all outer edges of the first cross-sectional area forming a rectangle;
and
a second intra-cell connection on the semiconductor substrate electrically coupling an active area of the second pass-gate transistor, an active area of the second pull-down transistor, and an active area of the second pull-up transistor to a gate of the first pull-up transistor and a gate of the first pull-down transistor, wherein the second intra-cell connection has a second cross-sectional area parallel to the top surface of the substrate, all outer edges of the first cross-sectional area forming a rectangle.

1 more element

Dependencies are inferred from the claim text.