Field effect transistor
AssigneeInternational Business Machines Corporation
InventorsToshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Charles W. Koburger, III
Life of this patent
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Abstract
A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions formed on opposite sides of the polysilicon gate electrode in the well region; a first doped region in the polysilicon gate electrode, the first doped region extending into the polysilicon gate electrode from a top surface of the polysilicon gate electrode; and a buried second doped region in the polysilicon gate electrode.
Claims27
A transistor, comprising:
- a well region formed in a substrate;
- a gate dielectric layer on a top surface of said well region;
- a polysilicon gate electrode on a top surface of said gate dielectric layer;
- spacers formed on opposite sidewalls of said polysilicon gate electrode, a height of said polysilicon gate electrode at least equal to a height of said spacers in a direction perpendicular to a top surface of said substrate, a region of a top surface of said polysilicon gate electrode exposed between said spacers;
- a plurality of carbon nanotubes formed on exposed surfaces of said spacers;
- source/drain regions formed on opposite sides of said polysilicon gate electrode in said well region.
A transistor:
- a well region in a substrate;
- a gate dielectric layer on a top surface of said well region;
- a polysilicon gate electrode on a top surface of said gate dielectric layer;
- spacers formed on opposite sidewalls of said polysilicon gate electrode, a region of a top surface of said polysilicon gate electrode exposed between said spacers;
- a plurality of carbon nanotubes formed on exposed surfaces of said spacers;
- source/drain regions formed on opposite sides of said polysilicon gate electrode in said well region;
- and
- a conformal layer directly on top of said plurality of carbon nanotubes, said conformal layer completely filling spaces between said plurality of carbon nanotubes.
Dependencies are inferred from the claim text.