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US 7,996,671 B2Granted
Security of program executables and microprocessors based on compiler-architecture interaction
AssigneeBlueRISC, Inc.
InventorsSaurabh Chheda, Kristopher Carver, Raksit Ashok
Life of this patent
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Abstract
A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction.
Claims42
A processor comprising:
- storage memory to store an instruction stream that corresponds to a single program executable, the instruction stream comprising coded control instructions and other coded instructions, at least some of the other coded instructions having different instruction set architectures, each of at least some of the coded control instructions comprising control information that defines a rule for use in decoding a corresponding other coded instruction that is located in a subsequent part of the instruction stream;
- and
- a single instruction-decoder comprising a static-decode part and an instruction-decode part, the static-decode part to decode a coded control instruction in the instruction stream to obtain control information from the coded control instruction, the control information being usable by the instruction-decode part to decode a corresponding other coded instruction in the instruction stream.
A processor comprising:
- storage memory to store coded instructions for an instruction stream that corresponds to a single program executable, at least some of the coded instructions being scrambled for security so that the instruction stream comprises at least two different instruction set architectures;
- and
- a single instruction-decoder to decode a first type of the coded instructions to produce control information that defines schemes according to which bits of one or more corresponding coded instructions of a second type are scrambled in the instruction stream, wherein the single instruction-decoder is configured according to a scheme defined in the control information for a coded instruction of the first type to decode a corresponding and succeeding coded instruction of the second type, the single instruction-decoder being part of a pipeline of the processor.
A processor comprising:
- storage memory to store an instruction stream that corresponds to a single program executable, the instruction stream comprising coded control instructions and other coded instructions that are scrambled for security resulting in least two different instructions set architectures;
- wherein coded control instructions in the instruction stream comprise control information defining schemes according to which bits of corresponding other coded instructions in the coded instruction stream are scrambled;
- and
- a single instruction-decoder, which is part of a pipeline of the processor, to decode other coded instructions in the instruction stream using control information from corresponding coded control instructions and information in the other coded instructions.
1 more element
A method for use in a processor, the method comprising:
- storing an instruction stream that corresponds to a single program executable, the instruction stream comprising coded control instructions and other coded instructions, at least some of the other coded instructions having different instruction set architectures, each of at least some of the coded control instructions comprising control information that defines a rule for use in decoding a corresponding other coded instruction that is located in a subsequent part of the instruction stream;
- and
- performing decoding using a single instruction-decoder comprised of a static decode part and an instruction-decode part, the static-decode part decoding a coded control instruction in the instruction stream to obtain control information from the coded control instruction, the control information being usable by the instruction-decode part to decode a corresponding other coded instruction in the instruction stream.
A method for use in a processor, the method comprising:
- storing coded instructions for an instruction stream that corresponds to a single program executable, at least some of the coded instructions being scrambled for security so that the instruction stream comprises at least two different instruction set architectures;
- and
- using a single instruction-decoder, decoding a first type of the coded instructions to produce control information that defines schemes according to which one or more corresponding coded instructions of a second type are scrambled in the instruction stream, wherein the single instruction-decoder is configured according to a scheme defined in the control information for a coded instruction of the first type to decode a corresponding and succeeding coded instruction of the second type, the single instruction-decoder being part of a pipeline of the processor.
A method for use in a processor, the method comprising:
- storing an instruction stream that corresponds to a single program executable, the instruction stream comprising coded control instructions and other coded instructions that are scrambled for security resulting in at least two different instruction set architectures;
- wherein coded control instructions in the instruction stream comprise control information defining schemes according to which bits of corresponding other coded instructions in the coded instruction stream are scrambled;
- and
- decoding instructions in the pipeline of the processor using a single instruction-decoder, wherein decoding comprises decoding other coded instructions in the instruction stream using control information from corresponding coded control instructions and information in the other coded instructions.
1 more element
A processor comprising:
- storing means for storing coded instructions for an instruction stream that corresponds to a single program executable, at least some of the coded instructions being scrambled for security so that the instruction stream comprises at least two different instruction set architectures;
- and
- decoding means comprising a single instruction-decoder for decoding a first type of the coded instructions to produce control information that defines schemes according to which bits of one or more corresponding coded instructions of a second type are scrambled in the instruction stream, wherein the single instruction-decoder is configured according to a scheme defined in the control information for a coded instruction of the first type to decode a corresponding and succeeding coded instruction of the second type, the single instruction-decoder being part of a pipeline of the processor.
A processor comprising:
- storing means for storing an instruction stream that corresponds to a single program executable, the instruction stream comprising coded control instructions and other coded instructions that are scrambled for security resulting in at least two different instruction set architectures;
- wherein coded control instructions in the instruction stream comprise control information defining schemes according to which bits of corresponding other coded instructions in the coded instruction stream are scrambled;
- and
- decoding means comprising a single instruction-decoder for decoding instructions in the pipeline of the processor, wherein decoding comprises decoding other coded instructions in the instruction stream using control information from corresponding coded control instructions and information in the other coded instructions.
1 more element
A processor comprising:
- storage means to store an instruction stream that corresponds to a single program executable, the instruction stream comprising coded control instructions and other coded instructions, at least some of the other coded instructions having different instruction set architectures, each of at least some of the coded control instructions comprising control information that defines a rule for use in decoding a corresponding other coded instruction that is located in a subsequent part of the instruction stream;
- and
- decoding means comprising a single instruction-decoder, the single instruction decoder comprising a static-decode part and an instruction-decode part, the static-decode part to decode a coded control instruction in the instruction stream to obtain control information from the coded control instruction, the control information being usable by the instruction-decode part to decode a corresponding other coded instruction in the instruction stream.
Dependencies are inferred from the claim text.