Clock and data recovery circuit

A clock and data recovery circuit comprising:

• a first feedback loop at least including:
• a voltage-controlled oscillator circuit varying an oscillation frequency based on a control signal voltage supplied thereto;
• a first phase detector circuit supplied with a clock signal output from said voltage-controlled oscillator circuit and with a received data signal to detect a phase difference between said clock signal and said received data signal;
• and
• a first integrator circuit integrating an output of said first phase detector circuit to supply an integrated signal to said voltage-controlled oscillator circuit as said control signal voltage;
• and
• a second feedback loop including:
• a discriminator circuit supplied with said received data signal, said discriminator circuit discriminating said received data signal, responsive to a discrimination clock signal supplied thereto;
• and
• a second phase detector circuit supplied with an output data signal discriminated and output by said discriminator circuit and with said received data signal to detect a phase difference between said two signals supplied;
• and
• a second integrator circuit integrating an output of said second phase detector circuit;
• and
• a phase shift circuit supplied with said clock signal output from said voltage-controlled oscillator circuit and with an integrated signal output from said second integrator circuit, said phase shift circuit shifting a phase of said clock signal supplied in accordance with said integrated signal output from said second integrator circuit, to output a resulting clock signal;
• said clock signal output from said phase shift circuit being supplied to said discriminator circuit, as said discrimination clock signal and being output as an output clock signal.

A clock and data recovery circuit comprising:

• a first feedback loop including:
• a voltage-controlled oscillator circuit varying an oscillation frequency based on a control signal voltage supplied thereto;
• a first phase detector circuit receiving a clock signal output from said voltage-controlled oscillator circuit and a reference clock signal to detect a phase difference therebetween;
• and
• a first integrator circuit integrating an output of said first phase detector circuit to supply an integrated signal to said voltage-controlled oscillator circuit as a control signal voltage;
• and
• a second feedback loop including:
• a discriminator circuit supplied with a received data signal, said discriminator circuit discriminating said received data signal, responsive to a discrimination clock signal supplied thereto;
• a second phase detector circuit supplied with an output data signal discriminated and output by said discriminator circuit and with said received data signal to detect a phase difference between said two signals supplied
• a second integrator circuit integrating an output of said second phase detector circuit;
• and
• a phase shift circuit supplied with said clock signal output from said voltage-controlled oscillator circuit and with an integrated signal output from said second integrator circuit, said phase shift circuit shifting a phase of said clock signal supplied in accordance with said integrated signal output from said second integrator circuit, to output a resulting clock signal;
• said clock signal output from said phase shift circuit being supplied to said discriminator circuit, as said discrimination clock signal and being output as an output clock signal.