Structure and method for fabricating self-aligned metal contacts
AssigneeInternational Business Machines Corporation
InventorsHuilong Zhu, Werner Rausch
Life of this patent
Estimating the term…
Abstract
A semiconductor structure including at least one transistor is provided which has a stressed channel region that is a result of having a stressed layer present atop a gate conductor that includes a stack comprising a bottom polysilicon (polySi) layer and a top metal semiconductor alloy (i.e., metal silicide) layer. The stressed layer is self-aligned to the gate conductor. The inventive structure also has a reduced external parasitic S/D resistance as a result of having a metallic contact located atop source/drain regions that include a surface region comprised of a metal semiconductor alloy. The metallic contact is self-aligned to the gate conductor.
Claims5
A method of forming a semiconductor structure comprising:
- providing a patterned material stack comprising a lower layer of polysilicon and an upper layer of polysilicon germanium on a surface of a semiconductor substrate, said patterned material stack having sidewalls that are covered by at least one spacer;
- removing said upper layer of polysilicon germanium from said patterned material stack;
- forming a first metal semiconductor alloy layer within said polysilicon layer and forming a second metal semiconductor alloy layer within said semiconductor substrate at a footprint of said at least one spacer;
- forming an etch stop liner and a stressed layer on said first semiconductor alloy layer, wherein said etch stop liner is present on a bottom surface and sidewall surfaces of said stressed layer;
- and
- forming a metallic contact comprising a metal from Group VIII or IB of the Periodic Table of Elements and at least one of W, B, P, Mo and Re on said second metal semiconductor alloy layer.
Dependencies are inferred from the claim text.