Reducing implant degradation in tilted implantations by shifting implantation masks

A method, comprising:

• providing a photolithography mask having a mask feature that is asymmetrically aligned to a first gate electrode structure;
• exposing a resist layer formed above a semiconductor region by using said photolithography mask, said semiconductor region having formed thereon said first gate electrode structure and a second gate electrode structure;
• forming an implantation mask from said exposed resist layer, said implantation mask covering said first gate electrode structure and exposing said second gate electrode structure, said implantation mask being asymmetrically shifted along a first transistor length direction;
• and
• forming a second implantation mask that is substantially symmetrically positioned above said second gate electrode structure with respect to said first length direction, wherein forming said second implantation mask comprises using a second photolithography mask having a second mask feature that is symmetrically aligned to said second gate electrode structure.

A method, comprising:

• providing a photolithography mask including a mask feature positioned symmetrically with respect to a location corresponding to a first gate electrode structure of a first transistor;
• aligning said photolithography mask with a predefined shift with respect to a transistor length direction of said first transistor;
• forming an implantation mask on the basis of said photolithography mask, said implantation mask being asymmetrically positioned above said first gate electrode structure and exposing a second gate electrode structure of a second transistor;
• and
• performing an implantation process on the basis of said implantation mask by using a tilt angle to form an asymmetric implantation region in said second transistor.

A method, comprising:

• forming an implantation mask above a semiconductor region to cover a portion of said semiconductor region and a first gate electrode structure of a first transistor formed on said semiconductor region, said implantation mask exposing a second gate electrode structure of a second transistor formed on said semiconductor region, said implantation mask being positioned above said first gate electrode structure in an asymmetric manner with respect to a transistor length orientation;
• implanting a first ion species into said semiconductor region by using a first non-zero tilt angle;
• and
• forming a second implantation mask to cover a portion of said semiconductor region and said second gate electrode structure and to expose said first gate electrode structure, wherein said second implantation mask is positioned above said second gate electrode structure in a substantially symmetric manner with respect to said transistor length orientation.