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US 7,968,976 B2Granted
Guard ring extension to prevent reliability failures
AssigneeIntel Corporation
InventorsNicole Meier Chang, George J. Korsh, Shafqat Ahmed, John M. Nugent, Ed Nabighian
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Abstract
An embodiment of the present invention is a technique to prevent reliability failures in semiconductor devices. A trench is patterned in a polyimide layer over a guard ring having a top metal layer. A passivation layer is etched at bottom of the trench. A capping layer is deposited on the trench over the etched passivation layer. The capping layer and the top metal layer form a mechanical strong interface to prevent a crack propagation.
Claims4
A semiconductor apparatus, comprising:
- an active die region;
- a guard ring having a plurality of stacked metal layers, the plurality of stacked metal layers including a top metal layer, the guard ring having an inner boundary closer to the active die region and an outer boundary further from the active die region;
- a first dielectric layer having a top boundary and a bottom boundary, at least some of the top metal layer being between the top and bottom boundaries of the first dielectric layer;
- a passivation layer over at least a portion of the top metal layer and at least a portion of the first dielectric layer;
- and
- a metal capping layer over the top metal layer, the metal capping layer comprising:
- a first portion proximate to the outer boundary of the guard ring and in direct contact with the first dielectric layer,
- a second portion proximate to the outer boundary and in direct contact with the top metal layer, and
- a third portion proximate to the inner boundary of the guard ring and separated from the top metal layer by the passivation layer.
6 more elements
Dependencies are inferred from the claim text.