Converting program code with access coordination for a shared memory
AssigneeInternational Business Machines Corporation
InventorsGavin Barraclough, Paul Knowles
Life of this patent
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Abstract
A dynamic binary translator 19 converts a subject program 17 into target code 21 on a target processor 13. For a multi-threaded subject environment, the translator 19 provides a global token 501 common to each thread 171, 172, and one or more sets of local data 502, which together are employed to coordinate access to a memory 18 as a shared resource. Adjusting the global token 501 allows the local datastructures 502a,b in each thread to detect potential interference with the shared resource 18.
Claims34
A method of providing an access coordination mechanism of a shared resource, comprising:
- (a) providing a plurality of local datastructures each associated with one of the multiple subject threads, and a global token common to each of the subject threads, wherein the multiple subject threads are executable on a subject processor, corresponding to a first processor type;
- (b) decoding the subject code to identify a subject setting instruction which sets a subject access coordination mechanism in relation to a shared resource, and a subject checking instruction which checks the subject access coordination mechanism;
- (c) in response to the subject setting instruction, generating target code for adjusting the global token, and storing at least a local token in the local datastructure for a current thread, wherein the local token is derived from the adjusted global token;
- (d) in response to the subject checking instruction, generating target code for execution on a target processor, corresponding to a second processor type, for comparing at least the stored local token against the global token to determine potential interference with the shared resource;
- and
- (e) in response to the comparison, clearing a reservation flag associated with the global token if a store-conditional instruction succeeded;
- wherein the first processor type is a different processor type than the second processor type.
A translator apparatus to perform program code conversion from subject code executable by a subject processor, corresponding to a first processor type, into target code executable by a target processor, corresponding to a second processor type, the apparatus comprising:
- the target processor having a memory storing a translation unit to translate subject code executable on a subject processor into translated target code for execution on the target processor, wherein the subject code includes multiple subject threads, wherein the translator unit
- a) provides a plurality of local datastructures each associated with one of the multiple subject threads, and a global token common to each of the subject threads;
- b) decodes the subject code to identify a subject setting instruction which sets a subject access coordination mechanism in relation to a shared resource, and a subject checking instruction which checks the subject access coordination mechanism;
- c) in response to the subject setting instruction, generates target code for adjusting the global token, and storing at least a local token in the local datastructure for a current thread, wherein the local token is derived from the adjusted global token;
- d) in response to the subject checking instruction, generates target code for comparing at least the stored local token against the global token to determine potential interference with the shared resource;
- and
- (e) in response to the comparison, clearing a reservation flag associated with the global token if a store-conditional instruction succeeded;
- and
- wherein the first processor type is a different processor type than the second processor type.
The translator apparatus 19, wherein the translation unit is arranged to detect a system call from the subject code or an interrupt affecting the subject code, and in response adjust the global token to show potential interference with the shared resource.
A computer-readable medium having recorded thereon instructions implementable by a computer to perform the method of providing an access coordination mechanism of a shared resource, for use in program code conversion from subject code having multiple subject threads into target code executable by a target processor, corresponding to a first processor type, the method including:
- (a) providing a plurality of local datastructures each associated with one of the multiple subject threads, and a global token common to each of the subject threads, wherein the subject treads are executable on a subject processor, corresponding to a second processor type;
- (b) decoding the subject code to identify a subject setting instruction which sets a subject access coordination mechanism in relation to a shared resource, and a subject checking instruction which checks the subject access coordination mechanism;
- (c) in response to the subject setting instruction, generating target code, executable on the target processor, for adjusting the global token, and storing at least a local token in the local datastructure for a current thread, wherein the local token is derived from the adjusted global token;
- (d) in response to the subject checking instruction, generating target code for comparing at least the stored local token against the global token to determine potential interference with the shared resource;
- and
- (e) in response to the comparison, clearing a reservation flag associated with the global token if a store-conditional instruction succeeded;
- wherein the first processor type is a different processor type than the second processor type.
Dependencies are inferred from the claim text.