Pulse control device
AssigneeHynix Semiconductor Inc.
InventorsKyoung-Nam Kim, Tae-Yun Kim
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Abstract
A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.
Claims16
A pulse control device comprising:
- a fuse set configured to control a coupling state of a fuse according to a process change information and to output a delay increase signal or a delay decrease signal;
- and
- a pulse generator having a delay controller configured to increase or decrease the number of a plurality of delay cells in response to the delay increase signal or the delay decrease signal to generate an internal clock having a constant pulse width irrespective of a process change:
- wherein the delay controller selectively transfers an output signal of a first delay cell or a reference clock to a second delay cell in response to the delay increase signal, and selectively outputs an output signal of the second delay cell or an output signal of a third delay cell, which delays the output signal of the second delay cell, in response to the delay decrease signal.
A pulse control device comprising:
- a fuse set configured to control a coupling state of a fuse according to a process change information and to output a delay increase signal or a delay decrease signal;
- and
- a pulse generator having a delay controller configured to increase or decrease the number of a plurality of delay cells in response to the delay increase signal or the delay decrease signal to generate an internal clock,
- wherein the delay controller logically combines a reference clock with a logical combination of an output signal of a first delay cell and the delay increase signal, outputs a logically combined result to a second delay cell, and logically combines a logical combination of an output signal of the second delay cell and the delay decrease signal with an output signal of a third delay cell delaying the output signal of the second delay cell.
Dependencies are inferred from the claim text.