Methods of designing an integrated circuit on corrugated substrate

A method of designing a transistor, the method comprising:

• forming a source;
• forming a drain;
• forming a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• forming a gate to wrap over each of the plurality of semiconductor ridges;
• adjusting a distance the gate wraps over each of the plurality of semiconductor ridges to provide a predetermined on-state drive current and a predetermined off-state source-to-drain leakage current;
• and
• forming a set of gate dielectrics, each gate dielectric covering a portion of the top surface of a semiconductor ridge and extending down sides of the semiconductor ridge by a first distance,
• wherein the gate is formed over the set of gate dielectrics and extends down the sides of the semiconductor ridges by substantially the first distance,
• wherein forming the plurality of semiconductor ridges includes providing at least one heavily doped channel region in each semiconductor ridge, and
• wherein the at least one heavily doped channel region reaches at least 50% of maximum dopant concentration below the first distance.

A method of designing a transistor, the method comprising:

• forming a source;
• forming a drain;
• forming a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• forming a gate to wrap over each of the plurality of semiconductor ridges;
• adjusting a distance the gate wraps over each of the plurality of semiconductor ridges to provide a predetermined on-state drive current and a predetermined off-state source-to-drain leakage current;
• forming a set of gate dielectrics, each gate dielectric covering a portion of the top surface of a semiconductor ridge and extending down sides of the semiconductor ridge by a first distance, wherein the gate is formed over the set of gate dielectrics and extends down the sides of the semiconductor ridges by substantially the first distance;
• and
• providing insulation material separating the plurality of semiconductor ridges,
• wherein the source comprises a first region doped to a first depth beneath top surfaces of the plurality of semiconductor ridges,
• wherein the drain comprises a second region doped to a second depth beneath the top surfaces of the plurality of semiconductor ridges, and
• wherein the insulation material reaches a third depth beneath the top surfaces of the plurality of semiconductor ridges, wherein the third depth is greater than the first depth and the second depth.

A method of designing a transistor, the method comprising:

• forming a source;
• forming a drain;
• forming a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• forming a gate to wrap over each of the plurality of semiconductor ridges;
• adjusting a distance the gate wraps over each of the plurality of semiconductor ridges to provide a predetermined on-state drive current and a predetermined off-state source-to-drain leakage current;
• forming a set of gate dielectrics, each gate dielectric covering a portion of the top surface of a semiconductor ridge and extending down sides of the semiconductor ridge by a first distance, wherein the gate is formed over the set of gate dielectrics and extends down the sides of the semiconductor ridges by substantially the first distance;
• and
• providing insulation material separating the plurality of semiconductor ridges,
• wherein the source comprises a first region doped to a first depth beneath top surfaces of the plurality of semiconductor ridges,
• wherein the drain comprises a second region doped to a second depth beneath the top surfaces of the plurality of semiconductor ridges, and
• wherein the insulation material reaches a third depth beneath the top surfaces of the plurality of semiconductor ridges, wherein the third depth is less than the first depth and the second depth.

A method of designing a transistor, the method comprising:

• forming a source;
• forming a drain;
• forming a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• forming a gate to wrap over each of the plurality of semiconductor ridges;
• adjusting a distance the gate wraps over each of the plurality of semiconductor ridges to provide a predetermined on-state drive current and a predetermined off-state source-to-drain leakage current;
• and
• forming a first sidewall spacer and a second sidewall spacer on either side of the gate,
• wherein the source comprises a first shallow extension under the first sidewall spacer and a remainder of the source being deeper than the first shallow extension, and
• wherein the drain comprises a second shallow extension under the second sidewall spacer and a remainder of the drain being deeper than the first shallow extension.

A method of designing a transistor, the method comprising:

• forming a source;
• forming a drain;
• forming a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• forming a gate to wrap over each of the plurality of semiconductor ridges;
• and
• adjusting a distance the gate wraps over each of the plurality of semiconductor ridges to provide a predetermined on-state drive current and a predetermined off-state source-to-drain leakage current,
• wherein forming the plurality of semiconductor ridges includes forming a first semiconductor material layer on a second semiconductor layer.

A method of designing a transistor, the method comprising:

• forming a source;
• forming a drain;
• forming a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• forming a gate to wrap over each of the plurality of semiconductor ridges;
• adjusting a distance the gate wraps over each of the plurality of semiconductor ridges to provide a predetermined on-state drive current and a predetermined off-state source-to-drain leakage current;
• and
• forming transistor isolation material below a base of the plurality of semiconductor ridges, wherein a depth of the transistor isolation material is at least equal to a height of the plurality of semiconductor ridges.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• and
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents,
• wherein providing the plurality of semiconductor ridges includes:
• providing the plurality of semiconductor ridges on an elevated semiconductor base that extends a predetermined height above adjacent substrate surfaces.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to foam a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents;
• and
• providing a set of gate dielectrics, each gate dielectric covering a portion of the top surface of a semiconductor ridge and extending down sides of the semiconductor ridge by a first distance,
• wherein the gate is formed over the set of gate dielectrics and extends down the sides of the semiconductor ridges by substantially the first distance,
• wherein providing the plurality of semiconductor ridges includes providing at least one heavily doped channel region in each semiconductor ridge, and,
• wherein the at least one heavily doped channel region reaches at least 50% of maximum dopant concentration below the first distance.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents;
• and
• providing insulation material separating the plurality of semiconductor ridges,
• wherein the source comprises a first region doped to a first depth beneath top surfaces of the plurality of semiconductor ridges,
• wherein the drain comprises a second region doped to a second depth beneath the top surfaces of the plurality of semiconductor ridges, and
• wherein the insulation material reaches a third depth beneath the top surfaces of the plurality of semiconductor ridges, wherein the third depth is greater than the first depth and the second depth.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents;
• and
• providing insulation material separating the plurality of semiconductor ridges,
• wherein the source comprises a first region doped to a first depth beneath top surfaces of the plurality of semiconductor ridges,
• wherein the drain comprises a second region doped to a second depth beneath the top surfaces of the plurality of semiconductor ridges, and
• wherein the insulation material reaches a third depth beneath the top surfaces of the plurality of semiconductor ridges, wherein the third depth is less than the first depth and the second depth.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents;
• and
• providing a first sidewall spacer and a second sidewall spacer on either side of the gate,
• wherein the source comprises a first shallow extension under the first sidewall spacer and a remainder of the source being deeper than the first shallow extension, and
• wherein the drain comprises a second shallow extension under the second sidewall spacer and a remainder of the drain being deeper than the first shallow extension.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• and
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents,
• wherein providing the plurality of semiconductor ridges includes providing a first semiconductor material layer on a second semiconductor layer.

A method of designing a transistor, the method comprising:

• providing a source;
• providing a drain;
• providing a plurality of semiconductor ridges connecting the source and the drain to form a channel region;
• providing a gate to wrap over each of the plurality of semiconductor ridges;
• determining a distance the gate wraps over each of the plurality of semiconductor ridges to provide desired on-state and off-state currents;
• and
• providing transistor isolation material below a base of the plurality of semiconductor ridges, wherein a depth of the transistor isolation material is at least equal to a height of the plurality of semiconductor ridges.