Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same

An integrated circuit device comprising:

• a memory cell array including:
• a plurality of memory cells arranged in a matrix of rows and columns, wherein each memory cell is programmable to store one of a plurality of data states;
• a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line;
• memory cell control circuitry, coupled to the memory cell array, to generate one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line;
• sense amplifier circuitry having an input which is electrically coupled to the bit line to receive a signal which is responsive to the current conducted on the bit line, and, in response thereto, to (i) sense the data state stored in the selected memory cell and (ii) output a signal which is representative thereof;
• current regulation circuitry, electrically coupled to the bit line, to sink or source at least a portion of the current conducted on the bit line by the selected memory cell during only a portion of the read operation;
• and
• sensing circuitry, coupled between the bit line and the current regulation circuitry, to responsively couple the current regulation circuitry to the bit line during only the portion of the read operation.

An integrated circuit device comprising:

• a memory cell array including:
• a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor;
• a bit line having an intrinsic capacitance, wherein a plurality of the memory cells are coupled to the bit line;
• means for generating one or more read control signals to perform a read operation wherein, in response to the one or more read control signals, the electrically floating body transistor associated with a selected memory cell conducts a current, which is representative of the data state stored in the selected memory cell, on the bit line;
• means for receiving a signal which is responsive to the current conducted on the bit line by the electrically floating body transistor of the selected memory cell and, in response thereto, for (i) sensing the data state stored in the selected memory cell and (ii) outputting a signal which is representative thereof;
• current regulation means for sinking or sourcing at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation;
• and
• means for responsively and electrically coupling the current regulation means to the bit line during only the portion of the read operation.

A method of reading a memory cell which is disposed on integrated circuit device comprising a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns, wherein the memory cell array includes a plurality of memory cells wherein each memory cell includes an electrically floating body transistor including a body region which is electrically floating, wherein each memory cell is programmable to store one of a plurality of data states including (i) a first data state representative of a first charge in the body region of the transistor, and (ii) a second data state representative of a second charge in the body region of the transistor, the method comprising:

• generating read control signals to perform a read operation wherein, in response to read control signals, the electrically floating body transistor associated of a selected memory cell conducts a current which is representative of the data state of the memory cell on a bit line;
• determining the data state stored in the selected memory cell using a signal which is responsive to the current conducted by the electrically floating body transistor and, in response thereto, outputting a data state signal which is representative of the data state of the memory cell on the bit line;
• sinking or sourcing at least a portion of the current conducted on the bit line by the electrically floating body transistor of the selected memory cell during only a portion of the read operation;
• and
• sensing a predetermined voltage on the bit line, wherein sinking or sourcing at least a portion of the current conducted on the bit line further includes sinking or sourcing a substantial portion of the current conducted on the bit line by the electrically floating body transistor after sensing the predetermined voltage on the bit line.