# US 7,951,649 B2 · Process for the collective fabrication of 3D electronic modules

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- Number: US 7,951,649 B2
- Document ID: US7951649B2
- Status: Granted
- Kind: B2
- Application number: 12/438,179
- Filed: 2007-08-03
- Published: 2009-08-20
- Granted: 2011-05-31
- Earliest claimed: 2006-08-22
- Assignees: 3D Plus
- Inventors: Christian Val
- Web page: https://patentgrep.com/patent/US7951649B2

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10D 86/01: Manufacture or treatment
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7434: {used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate}
- H10P 72/7442: {Separation by peeling}
- H10W 72/834: {Interconnections on sidewalls of chips}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/722: {between stacked chips}
- Y10T 29/49004: including measuring or testing of device or component part
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer. The components are encapsulated in an insulating resin (6) of thickness er, filling the spaces between the components, then separated from one another by first grooves (30) with a width L1 and a depth P1 such that ei+er<P1<ei+er+es, the connection pads of components (2) being connected to tracks (3) that are flush with the grooves (30); B1) a step of depositing an adhesive support (40) on the component-side face; C1) a step of removing the silicon wafer (10) so as to expose the test pads (20); D1) a step of electrically testing the components of the wafer via the test pad (20) and of marking the valid components (11′) and/or defective components; and E1) a step of bonding the dies (50) onto an adhesive film (41), each die comprising a valid component (11′) connected to test pads (20) and to at least one track (3), insulating resin (6), and an insulating layer (4), the dies being separated by second grooves (31) of width L2 with which the connection tracks (3) of the valid components (11′) are flush. This step, repeated K times, is followed by a step of stacking the K wafers, of forming metallized holes in the thickness of the stack, which are intended for connecting the dies together, and then of dicing the stack in order to obtain the n 3D modules.

## Claims

### Claim 1

Process for the fabrication of n electronic modules, n being an integer greater than 1, a module having a stack of K electronic dies, a die i, i varying from 1 to K, having at least one electronic component on an insulating substrate, the K dies being electrically connected together by conductors located on the lateral faces of the stack, fabrication is collective comprising:
a first step having, for each die i, of:
A1) a step of fabricating a batch of n dies i on one and the same thin plane wafer of thickness es having silicon, covered on one face with electrical connection test pads, and then with a thin electrically insulating layer of thickness ei, forming the insulating substrate and provided with at least one silicon electronic component having connection pads connected to the test pads through said insulating layer, the components being encapsulated in an insulating resin of thickness er, filling the spaces between the components, then separated from one another by first grooves with a width L1 and a depth P1 such that ei+e r<P1 <ei+er+es, the connection pads of the components being connected to tracks that are flush with the grooves;
B1) a step of depositing an adhesive support on the component-side face;
C1) a step of removing the silicon wafer so as to expose the test pads;
D1) a step of electrically testing the components of the wafer via the test pads and of marking the valid components and/or defective components; and
E1) a step of bonding the dies onto an adhesive film, each die comprising a valid component connected to test pads and to at least one track, insulating resin, and an insulating layer, the dies being separated by second grooves of width L2 with which the connection tracks of the valid components are flush; and
a second step consisting in:
A2) stacking and assembling the K batches obtained after the first step, so as to superpose the second grooves, substantially one ontop of another;
B2) forming third grooves in the stacks at the second grooves, with a width L3≧L2; and
C2) interconnecting the dies at the wall of the third grooves.

### Claim 2 (depends on 1)

Process according to claim 1, wherein L2<L1.

### Claim 3 (depends on 1)

Process according to claim 1, including, prior to the step of depositing an adhesive support on the component-side face, a step of thinning that face of the wafer comprising the components by surfacing.

### Claim 4 (depends on 1)

Process according to claim 1, wherein step C2 comprises the steps comprising:
metallizing the wall of the third grooves by means of a metal layer; and
forming a die interconnection scheme in said metal layer.

### Claim 5 (depends on 1)

Process according to claim 1, wherein the stacking of step A2 is carried out on a support.

### Claim 6 (depends on 1)

Process according to claim 1, wherein the electronic component is an active or passive component or an MEMS.

### Claim 7 (depends on 6)

Process according to claim 6, wherein the active component is a chip.

### Claim 8 (depends on 1)

Process according to claim 1, wherein least one passive component is located in the wafer or on the wafer.

### Claim 9 (depends on 2)

Process according to claim 2, including, prior to the step of depositing an adhesive support on the component-side face, a step of thinning that face of the wafer comprising the components by surfacing.

### Claim 10 (depends on 2)

Process according to claim 2, step C2 comprises the steps comprising:
metallizing the wall of the third grooves by means of a metal layer; and
forming a die interconnection scheme in said metal layer.

### Claim 11 (depends on 3)

Process according to claim 3, step C2 comprises the steps comprising:
metallizing the wall of the third grooves by means of a metal layer; and
forming a die interconnection scheme in said metal layer.

### Claim 12 (depends on 2)

Process according to claim 2, wherein the stacking of step A2 is carried out on a support.

### Claim 13 (depends on 3)

Process according to claim 3, wherein the stacking of step A2 is carried out on a support.

### Claim 14 (depends on 4)

Process according to claim 4, wherein the stacking of step A2 is carried out on a support.

### Claim 15 (depends on 2)

Process according to claim 2, wherein the electronic component is an active or passive component or an MEMS.

### Claim 16 (depends on 3)

Process according to claim 3, wherein the electronic component is an active or passive component or an MEMS.

### Claim 17 (depends on 4)

Process according to claim 4, wherein the electronic component is an active or passive component or an MEMS.

### Claim 18 (depends on 5)

Process according to claim 5, wherein the electronic component is an active or passive component or an MEMS.

### Claim 19 (depends on 2)

Process according to claim 2, wherein least one passive component is located in the wafer or on the wafer.

### Claim 20 (depends on 3)

Process according to claim 3, wherein least one passive component is located in the wafer or on the wafer.