US 7,949,855 B1Granted

Scheduler in multi-threaded processor prioritizing instructions passing qualification rule

AssigneeNVIDIA Corporation

InventorsPeter C. Mills, John Erik Lindholm, Brett W. Coon, Gary M. Tarolli, John Matthew Burgess

Life of this patent

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Abstract

A processor buffers asynchronous threads. Instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one computation operation and at least one memory access operation. Instructions within each phase are qualified and prioritized. The instructions may be qualified based on the status of the execution unit needed to execute one or more of the current instructions. The instructions may also be qualified based on an age of each instruction, status of the execution units, a divergence potential, locality, thread diversity, and resource requirements. Qualified instructions may be prioritized based on execution units needed to execute instructions and the execution units in use. One or more of the prioritized instructions is issued per cycle to the plurality of execution units.

Claims20

Dependent claims

A multi-threaded processor, comprising:

a plurality of different types of execution units, at least one of each type of execution unit servicing a different class of operations;
an instruction buffer that is configured to buffer a set of instructions for a plurality of asynchronous threads, each instruction requiring an operation performed by one of each of the plurality of different types of execution units;
a monitor unit coupled to the plurality of different types of execution units and configured to monitor status of the plurality of different types of execution units;
and
an instruction scheduler coupled to the instruction buffer and the monitor unit, configured to receive input from the instruction buffer and the monitor unit, and also configured to:
qualify at least a portion of the set of instructions for execution based on a qualification rule stored in memory and the status of the plurality of different types of execution units to produce a set of qualified instructions;
wherein a remaining portion of the set of instructions are unqualified for execution based on the qualification rule and the status of the plurality of different types of execution units;
prioritize the set of qualified instructions, and not the unqualified instructions, based on a prioritization rule to produce prioritized instructions for issue from said instruction buffer to the plurality of different types of execution units;
and
provide an output representing at least a portion of the prioritized instructions to be issued to at least a portion of the plurality of different types of execution units.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/110,942Filed 28 Apr 2008 · continuation
Priority: 17 Nov 2004
Granted: 24 May 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/3838
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: dependency mechanisms, e.g. register scoreboarding
G06F 9/3853
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: of compound instructions
G06F 9/3867
Concurrent instruction execution, e.g. pipeline or look ahead: using instruction pipelines

Family

Application10/991,640Parent of this continuation-in-part · filed 17 Nov 2004
Application11/404,196Parent of this continuation · filed 13 Apr 2006
US 7,366,878 B1Parent of this continuation · filed 29 Apr 2008
US 7,418,576 B1Parent of this continuation-in-part · filed 26 Aug 2008
Application11/404,196Parent of this continuation-in-part
US 7,949,855 B1This patent

From the US filing history. Foreign family members aren’t listed.