US 7,949,699 B1 · Implementation of decimation filter in integrated circuit device using ram-based data storage

Abstract

A programmable integrated circuit device such as a programmable logic device can be configured as a finite impulse response (FIR) filter capable of operating in decimation mode. The device includes at least one user-configurable random access memory block, and that user-configurable random access memory is configured as coefficient memories and data sample memories. The memories are large enough to hold up to all of the coefficients of the filter and a plurality of data samples at one time. Because the data samples and coefficients need not be shifted through the filter at the programmable logic device clock rate, overclocking of the filter is not necessary. The filter can run at a clock rate which is the same as the input data rate, while taking advantage of the available random access memory to mimic a shift register.

Claims19

Dependent claims

A FIR filter structure for operating in decimation filter mode;

said FIR filter structure comprising:
a first number of multipliers each corresponding to one or more taps of said FIR filter structure, each of said multipliers having first and second multiplicand inputs;
a second number of coefficient memories, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients;
and
a fourth number of data sample memories, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples;
wherein:
all of said multipliers, said coefficient memories, and said data sample memories operate at a single clock rate.

4 more elements

An integrated circuit device configured as a FIR filter for operating in one of decimation filter mode, said integrated circuit device having a plurality of multipliers and at least one user-configurable block of random access memory and comprising:

a first number of multipliers each corresponding to one or more taps of said FIR filter, each of said multipliers having first and second multiplicand inputs;
a second number of coefficient memories configured from said at least one user-configurable block of random access memory, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients;
and
a fourth number of data sample memories configured from said at least one user-configurable block of random access memory, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples;
wherein:
all of said multipliers, said coefficient memories, and said data sample memories operate at a single clock rate.

3 more elements

A method of programmably configuring an integrated circuit device as a FIR filter for operating in decimation filter mode, said integrated circuit device having a plurality of multipliers and at least one user-configurable block of random access memory, said method comprising:

programmably configuring a first number of multipliers to each correspond to one or more taps of said FIR filter, each of said multipliers having first and second multiplicand inputs;
programmably configuring a second number of coefficient memories from said at least one user-configurable block of random access memory, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients;
programmably configuring a fourth number of data sample memories from said at least one user-configurable block of random access memory, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples;
and
programmably configuring data read patterns for reading said data samples and said coefficients from said at least one user-configurable random access memory in an order corresponding to shifting of said data samples and said coefficients through said FIR filter.

2 more elements

A data storage medium encoded with machine-executable instructions for performing a method of programmably configuring an integrated circuit device as a FIR filter for operating in decimation filter mode, said integrated circuit device having a plurality of multipliers and at least one user-configurable block of random access memory, said method comprising:

programmably configuring a first number of multipliers to each correspond to one or more taps of said FIR filter, each of said multipliers having first and second multiplicand inputs;
programmably configuring a second number of coefficient memories from said at least one user-configurable block of random access memory, each respective one of said coefficient memories being connected to said first multiplicand input of a respective one of said multipliers, and having capacity to store a third number of coefficients;
programmably configuring a fourth number of data sample memories from said at least one user-configurable block of random access memory, each respective one of said data sample memories being connected to said second multiplicand input of a respective one of said multipliers, and having capacity to store a fifth number of data samples;
and
programmably configuring data read patterns for reading said data samples and said coefficients from said at least one user-configurable random access memory in an order corresponding to shifting of said data samples and said coefficients through said FIR filter.

2 more elements

Dependencies are inferred from the claim text.

Implementation of decimation filter in integrated circuit device using ram-based data storage

Life of this patent

Implementation of decimation filter in integrated circuit device using ram-based data storage

Life of this patent

Abstract

Claims19