Semiconductor device having 1965 nm gate electrode level region including at least four active linear conductive segments and at least one non-gate linear conductive segment

#This application is related to each application identified in the table below. The disclosure of each application identified in the table below is incorporated herein by reference in its entirety.

#Attorney Application Filing Docket No. Title No. Date BECKP004B Semiconductor Device with Dynamic 12/013,342 Jan. 11, 2008 Array Section BECKP004C Methods for Designing Semiconductor 12/013,356 Jan. 11, 2008 Device with Dynamic Array Section BECKP004D Methods for Defining Dynamic Array 12/013,366 Jan. 11, 2008 Section with Manufacturing Assurance Halo and Apparatus Implementing the Same TELAP014 Enforcement of Semiconductor 12/363,705 Jan. 30, 2009 Structure Regularity for Localized Transistors and Interconnect TELAP015A Cross-Coupled Transistor Layouts Using 12/402,465 Mar. 11, 2009 Linear Gate Level Features TELAP016 Defining and Using Contact Grids in 12/399,948 Mar. 7, 2009 Circuit Using Dynamic Array Architecture TELAP017 Methods for Multi-Wire Routing and 12/411,249 Mar. 25, 2009 Apparatus Implementing Same TELAP018 Co-Optimized Nano-Patterns for 12/484,130 Jun. 12, 2009 Integrated Circuit Design TELAP019 Methods for Defining and Utilizing Sub- 12/479,674 Jun. 5, 2009 Resolution Features in Linear Topology TELAP020 Optimizing Layout of Irregular 12/481,445 Jun. 9, 2009 Structures in Regular Layout Context TELAP021 Methods for Cell Phasing in Grid-Based 12/497,052 Jul. 2, 2009 Architecture and Apparatus Implementing Same TELAP022A Use of Oversized Contacts and Vias in a 12/466,335 May 14, 2009 Linearly Constrained Topology TELAP022B Use of Oversized Contacts and Vias in a 12/466,341 May 14, 2009 Linearly Constrained Topology TELAP023 Methods for Controlling Microloading 12/512,932 Jul. 30, 2009 Variation in Semiconductor Wafer Layout and Fabrication TELAP048 Circuitry and Layouts for XOR and 12/435,672 May 5, 2009 XNOR Logic TELAP004AC2 Semiconductor Device Layout Having 12/561,207 Sept. 16, 2009 Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions TELAP004AC3 Semiconductor Device Layout Including 12/561,216 Sept. 16, 2009 Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding Non-Symmetric Diffusion Regions TELAP004AC4 Semiconductor Device Layout Having 12/561,220 Sept. 16, 2009 Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors TELAP004AC6 Semiconductor Device Layout Having 12/561,229 Sept. 16, 2009 Restricted Layout Region Including Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors TELAP004AC7 Semiconductor Device Layout Including 12/561,234 Sept. 16, 2009 Cell Layout Having Restricted Gate Electrode Level Layout with Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors TELAP004AC8 Semiconductor Device Portion Having 12/561,238 Sept. 16, 2009 Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non- Symmetric Diffusion Regions TELAP004AC9 Semiconductor Device Portion Having 12/561,243 Sept. 16, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions TELAP004AC10 Semiconductor Device Portion Having 12/561,246 Sept. 16, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks and Having Corresponding Non-Symmetric Diffusion Regions TELAP004AC11 Semiconductor Device Portion Having 12/561,247 Sept. 16, 2009 Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors TELAP004AC12 Semiconductor Device Portion Having 12/563,031 Sept. 18, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors TELAP004AC13 Semiconductor Device Portion Having 12/563,042 Sept. 18, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having Equal Number of PMOS and NMOS Transistors TELAP004AC14 Semiconductor Device Portion Having 12/563,051 Sept. 18, 2009 Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors TELAP004AC15 Semiconductor Device Portion Having 12/563,056 Sept. 18, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors TELAP004AC16 Semiconductor Device Portion Having 12/563,061 Sept. 18, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Having At Least Eight Transistors TELAP004AC17 Semiconductor Device Layout Having 12/563,063 Sept. 18, 2009 Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions TELAP004AC18 Semiconductor Device Layout Including 12/563,066 Sept. 18, 2009 Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to- End Spacing with Corresponding Non- Symmetric Diffusion Regions TELAP004AC19 Semiconductor Device Layout Having 12/563,074 Sept. 18, 2009 Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to- End Spacing and Equal Number of PMOS and NMOS Transistors TELAP004AC20 Semiconductor Device Layout Including 12/563,076 Sept. 18, 2009 Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors TELAP004AC21 Semiconductor Device Layout Having 12/563,077 Sept. 18, 2009 Restricted Layout Region Including Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to- End Spacing and At Least Eight Transistors TELAP004AC22 Semiconductor Device Layout Including 12/567,528 Sept. 25, 2009 Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors TELAP004AC23 Semiconductor Device Portion Having 12/567,555 Sept. 25, 2009 Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non- Symmetric Diffusion Regions TELAP004AC24 Semiconductor Device Portion Having 12/567,565 Sept. 25, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions TELAP004AC25 Semiconductor Device Portion Having 12/567,574 Sept. 25, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding Non-Symmetric Diffusion Regions TELAP004AC26 Semiconductor Device Portion Having 12/567,574 Sept. 25, 2009 Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors TELAP004AC27 Semiconductor Device Portion Having 12/567,586 Sept. 25, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to- End Spacing and Having Equal Number of PMOS and NMOS Transistors TELAP004AC28 Semiconductor Device Portion Having 12/567,597 Sept. 25, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors TELAP004AC29 Semiconductor Device Portion Having 12/567,602 Sept. 25, 2009 Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors TELAP004AC30 Semiconductor Device Portion Having 12/567,609 Sept. 25, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to- End Spacing and Having At Least Eight Transistors TELAP004AC31 Semiconductor Device Portion Having 12/567,616 Sept. 25, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors TELAP004AC32 Layout of Cell of Semiconductor Device 12/567,623 Sept. 25, 2009 Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks TELAP004AC33 Layout of Cell of Semiconductor Device 12/567,630 Sept. 25, 2009 Having Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Corresponding p-type and n- type Diffusion Regions Separated by Central Inactive Region TELAP004AC34 Layout of Cell of Semiconductor Device 12/567,634 Sept. 25, 2009 Having Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors TELAP004AC35 Layout of Cell of Semiconductor Device 12/567,641 Sept. 25, 2009 Having Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors with Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region TELAP004AC36 Layout of Cell of Semiconductor Device 12/567,648 Sept. 25, 2009 Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors TELAP004AC37 Layout of Cell of Semiconductor Device 12/567,654 Sept. 25, 2009 Having Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors with Corresponding p- type and n-type Diffusion Regions Separated by Central Inactive Region TELAP004AC38 Cell of Semiconductor Device Having 12/571,343 Sept. 30, 2009 Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks TELAP004AC39 Cell of Semiconductor Device Having 12/571,351 Sept. 30, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks TELAP004AC40 Cell of Semiconductor Device Having 12/571,357 Sept. 30, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks TELAP004AC41 Cell of Semiconductor Device Having 12/571,998 Oct. 1, 2009 Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors TELAP004AC42 Cell of Semiconductor Device Having 12/572,011 Oct. 1, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors TELAP004AC43 Cell of Semiconductor Device Having 12/572,022 Oct. 1, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and Equal Number of PMOS and NMOS Transistors TELAP004AC44 Cell of Semiconductor Device Having 12/572,046 Oct. 1, 2009 Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors TELAP004AC45 Cell of Semiconductor Device Having 12/572,055 Oct. 1, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors TELAP004AC46 Cell of Semiconductor Device Having 12/572,061 Oct. 1, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors TELAP004AC47 Layout of Cell of Semiconductor Device 12/572,068 Oct. 1, 2009 Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing TELAP004AC48 Layout of Cell of Semiconductor Device 12/572,077 Oct. 1, 2009 Having Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region TELAP004AC49 Layout of Cell of Semiconductor Device 12/572,091 Oct. 1, 2009 Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors TELAP004AC50 Layout of Cell of Semiconductor Device 12/572,194 Oct. 1, 2009 Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having Equal Number of PMOS and NMOS Transistors and Having Corresponding p- type and n-type Diffusion Regions Separated by Central Inactive Region TELAP004AC51 Layout of Cell of Semiconductor Device 12/572,201 Oct. 1, 2009 Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors TELAP004AC52 Layout of Cell of Semiconductor Device 12/572,212 Oct. 1, 2009 Having Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Having At Least Eight Transistors and Having Corresponding p-type and n-type Diffusion Regions Separated by Central Inactive Region TELAP004AC53 Cell of Semiconductor Device Having 12/572,218 Oct. 1, 2009 Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing TELAP004AC54 Cell of Semiconductor Device Having 12/572,221 Oct. 1, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing TELAP004AC55 Cell of Semiconductor Device Having 12/572,225 Oct. 1, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing TELAP004AC56 Cell of Semiconductor Device Having 12/572,228 Oct. 1, 2009 Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors TELAP004AC57 Cell of Semiconductor Device Having 12/572,229 Oct. 1, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to- End Spacing and Equal Number of PMOS and NMOS Transistors TELAP004AC58 Cell of Semiconductor Device Having 12/572,232 Oct. 1, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and Equal Number of PMOS and NMOS Transistors TELAP004AC59 Cell of Semiconductor Device Having 12/572,237 Oct. 1, 2009 Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors TELAP004AC60 Cell of Semiconductor Device Having 12/572,239 Oct. 1, 2009 Sub-Wavelength-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to- End Spacing and At Least Eight Transistors TELAP004AC61 Cell of Semiconductor Device Having 12/572,243 Oct. 1, 2009 Sub-193 Nanometers-Sized Gate Electrode Conductive Structures Formed from Linear Shaped Gate Electrode Layout Features Defined with Minimum End-to-End Spacing and At Least Eight Transistors

#A push for higher performance and smaller die size drives the semiconductor industry to reduce circuit chip area by approximately 50% every two years. The chip area reduction provides an economic benefit for migrating to newer technologies. The 50% chip area reduction is achieved by reducing the feature sizes between 25% and 30%. The reduction in feature size is enabled by improvements in manufacturing equipment and materials. For example, improvement in the lithographic process has enabled smaller feature sizes to be achieved, while improvement in chemical mechanical polishing (CMP) has in-part enabled a higher number of interconnect layers.

#FIG. 1 is an illustration showing a number of neighboring layout features and a representation of light intensity used to render each of the layout features, in accordance with one embodiment of the present invention;

#FIG. 2 is an illustration showing a generalized stack of layers used to define a dynamic array architecture, in accordance with one embodiment of the present invention;

#FIG. 3A is an illustration showing an exemplary base grid to be projected onto the dynamic array to facilitate definition of the restricted topology, in accordance with one embodiment of the present invention;

#In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present invention.

#Generally speaking, a dynamic array architecture is provided to address semiconductor manufacturing process variability associated with a continually increasing lithographic gap. In the area of semiconductor manufacturing, lithographic gap is defined as the difference between the minimum size of a feature to be defined and the wavelength of light used to render the feature in the lithographic process, wherein the feature size is less than the wavelength of the light. Current lithographic processes utilize a light wavelength of 193 nm. However, current feature sizes are as small as 65 nm and are expected to soon approach sizes as small as 45 nm. With a size of 65 nm, the shapes are three times smaller than the wavelength of the light used to define the shapes. Also, considering that the interaction radius of light is about five light wavelengths, it should be appreciated that shapes exposed with a 193 nm light source will influence the exposure of shapes approximately 5*193 nm (1965 nm) away. When considering the 65 nm sized features with respect to 90 nm sized features, it should be appreciated that approximately two times as many 65 nm sizes features may be within the 1965 nm interaction radius of the 193 nm light source as compared to the 90 nm sized features.

#Due to the increased number of features within the interaction radius of the light source, the extent and complexity of light interference contributing to exposure of a given feature is significant. Additionally, the particular shapes associated with the features within the interaction radius of the light source weighs heavily on the type of light interactions that occur. Traditionally, designers were allowed to define essentially any two-dimensional topology of feature shapes so long as a set of design rules were satisfied. For example, in a given layer of the chip, i.e., in a given mask, the designer may have defined two-dimensionally varying features having bends that wrap around each other. When such two-dimensionally varying features are located in neighboring proximity to each other, the light used to expose the features will interact in a complex and generally unpredictable manner. The light interaction becomes increasingly more complex and unpredictable as the feature sizes and relative spacing become smaller.