Method and apparatus for calibrating internal pulses in an integrated circuit
AssigneeInternational Business Machines Corporation
InventorsRajiv V. Joshi, Robert L. Franch, Robert Maurice Houle, Kevin A. Batson
Life of this patent
Estimating the term…
Abstract
A method and circuit for measuring internal pulses includes an enable circuit configured to receive a control signal from an on-chip built-in tester to enable measurement of internal circuits. A delay chain is configured to receive a pulse signal from an on-chip circuit component. Sampling latches each include a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
Claims20
A circuit comprising:
- an enable circuit configured to select a clock signal in response to a control signal received from an on-chip built-in tester to enable measurement of internal circuits;
- a delay chain configured to receive a pulse signal from an on-chip circuit component being tested;
- and
- sampling latches, each having a data input coupled between adjacent delay elements of the delay chain and synchronized with the clock signal such that a transition in the pulse signal is indicated by comparing adjacent digital values in an output sequence.
A circuit comprising:
- a multiplexer configured to switch an output between a clock signal and a pulse signal for internal signals of an integrated circuit to be tested;
- an inverter chain configured to receive the output of the multiplexer;
- and
- sampling latches, each having a data input coupled between adjacent inverters in the inverter chain and synchronized with the clock signal;
- a logic gate configured to logically combine sampling latch outputs for two adjacent sampling latches such that transitions in the clock signal and the pulse signal are indicated by comparing the sampling latch outputs;
- and
- accumulating latches coupled to the sampling latches, the accumulating latches outputting a bit in a bit sequence to indicate the transition.
Dependencies are inferred from the claim text.