# US 7,940,839 B2 · Fully adaptive equalization for high loss communications channels

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- Number: US 7,940,839 B2
- Document ID: US7940839B2
- Status: Granted
- Kind: B2
- Application number: 10/597,455
- Filed: 2005-01-26
- Published: 2008-10-23
- Granted: 2011-05-10
- Earliest claimed: 2005-01-26
- Assignees: Diablo Technologies Inc.
- Inventors: Marcel Lapointe; Albert Vareljian; Riccardo Badalone
- Web page: https://patentgrep.com/patent/US7940839B2

## CPC

- H04B 3/04: Control of transmission; Equalising
- H04L 25/0307: {using blind adaptation}
- H04L 25/03343: {Arrangements at the transmitter end}
- H04L 25/03885: {adaptive}
- H04L 25/03159: {operating in the frequency domain (H04L25/03165, H04L25/03178 take precedence)}
- H04L 2025/03356: {Baseband transmission}
- H04L 2025/03636: {Algorithms using least mean square [LMS]}
- H04B: TRANSMISSION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An equalization circuit is disclosed that enables high data rate transmission over high loss communications channels. Also disclosed is a set of functional blocks and update criteria that allow for the equalization function to be adapted for a large variety of different communications channels. A fully continuous adaptive equalizer is used in conjunction with a Decision Feedback Equalizer to fully equalize a large number of communications channels.

## Claims

### Claim 1

An equalization apparatus for automatically equalizing serial communication over a communication channel comprising:
i) an adaptive transmit equalizer to receive an outgoing serial data stream and provide launch data into the communication channel, the launch data equalized in response to transmit control parameters;
ii) an adaptive receive equalizer to receive an incoming data stream from the communication channel and condition the received incoming data stream to produce an equalized output serial data stream in response to receive control parameters; and
iii) control means operable to control said adaptive transmit equalizer and said adaptive receive equalizer based on said incoming data stream;
wherein the adaptive receive equalizer includes an adaptive linear equalizer in combination with an adaptive non-linear decision feedback equalizer (DFE) to condition the received incoming data into said equalized output serial data stream; and
wherein the control means includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream wherein the demultiplexers provide inputs for producing said transmit control parameters and said receive control parameters.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the adaptive transmit equalizer has a symbol spaced feed forward equalizer with two taps corresponding to a cursor and pre-cursor.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the adaptive transmit equalizer has a two co-efficient Finite Impulse Response (FIR) filter symbol spaced feed forward equalizer with two taps corresponding to a cursor and pre-cursor the output of which is the launch data.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the adaptive transmit equalizer has a symbol spaced feed forward equalizer with a tap corresponding to a cursor and M pre-cursor taps.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the adaptive transmit equalizer has an M co-efficient Finite Impulse Response VA) filter that sums a portion of a cursor and the output of a symbol spaced feed forward equalizer with M taps, each tap corresponding to a successively earlier pre-cursor up to an Mth pre-cursor to produce the launch data.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein said linear equalizer includes two distinct signal paths to condition the received incoming data, one signal path is a controllable pure gain stage and the other signal path is independently controllable pure gain stage coupled to a high-pass filter, the combined output of both is gain adjusted and supplied to said adaptive non-linear decision feedback equalizer (DFE).

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein said DFE has a plurality of symbol spaced taps, each of which can be programmed independently.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the control means includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream wherein said transmit control parameters and receive control parameters are determined by the bit values.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein the control means includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a bit offset generator to define a window of data wherein said transmit control parameters and receive control parameters are determined by the bit values in said window of data.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the control means includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a pseudo random bit offset generator to define a window of data wherein said transmit control parameters and receive control parameters are determined by the bit values in said window of data.

### Claim 11

An equalization apparatus for automatically equalizing serial communication over a communication channel comprising:
i) an adaptive transmit equalizer including a symbol spaced feed forward equalizer with a first tap to condition a cursor symbol corresponding to a tap parameter C0 and M additional taps to condition each successively earlier pre-cursor symbol corresponding to a respective tap parameter C−M . . . C−1 to receive an outgoing serial data stream and output launch data into the communication channel;
ii) an adaptive receive equalizer to receive an incoming data stream from the communication channel including:
a controllable filter including a high-pass filter coupled to a controllable pure gain stage to condition the received incoming data stream corresponding to a gain parameter GHF ;
a summing node to sum the output of said controllable filter with the received incoming data stream that is gain adjusted corresponding to a gain parameter GDC;
a controllable pure gain stage coupled to the output of said summing node to provide an output at a gain corresponding to a gain parameter GAGC;
an N tap adaptive non-linear decision feedback equalizer (DFE) coupled to the output of the GAGC stage providing N symbol spaced taps, each of which can be programmed independently corresponding to a respective tap parameter C1, C2 . . . CN; and
iii) a demux and tap update block controller coupled to the output of said adaptive receive equalizer to produce said gain and tap parameters GHF, GAGC and C−1 , C0 . . . CN.

### Claim 12 (depends on 11)

The apparatus of claim 11 wherein said demux and tap update block controller further includes a data slicer, a positive offset monitor slicer and a negative offset monitor slicer each coupled to the output of said adaptive receiver.

### Claim 13 (depends on 11)

The apparatus of claim 11 wherein said demux and tap update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream wherein the demultiplexers provide inputs for producing said gain and tap parameters.

### Claim 14 (depends on 11)

The apparatus of claim 11 wherein said demux and tap update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream and a bit offset generator to define a window of data in said data demultiplexer, said positive monitor demultiplexer and said negative monitor demultiplexer wherein said gain and tap parameters are determined by the bit values in said window of data.

### Claim 15 (depends on 11)

The apparatus of claim 11 wherein said demux and tap update block controller includes a data slicer providing input to a data demultiplexer, a positive offset monitor slicer providing input to a positive monitor demultiplexer and a negative offset monitor slicer providing input to a negative monitor demultiplexer, each slicer coupled to said equalized output serial data stream and a pseudo random bit offset generator to define a window of data in said data demultiplexer, said positive monitor demultiplexer and said negative monitor demultiplexer wherein said gain and tap parameters are determined by the bit values in said window of data.

### Claim 16 (depends on 11)

The apparatus of claim 11 wherein said demux and tap update block controller includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a bit offset generator to define a window of data in said data word, said positive monitor word and said negative monitor word wherein said gain and tap parameters are determined by the bit values.

### Claim 17 (depends on 11)

The apparatus of claim 11 wherein said demux and tap update block controller includes a data word to store data channel bits, a positive monitor word to store positive monitor channel bits and a negative monitor word to store negative monitor channel bits, each said word stores bits responsive to the output of a respective slicer coupled to said equalized output serial data stream and a pseudo random bit offset generator to define a window of data in said data word, said positive monitor word and said negative monitor word wherein said gain and tap parameters are determined by the bit values.

### Claim 18

A method for automatically equalizing serial communication over a communication channel comprising the steps of:
i) using an M tap feed forward equalizer to shape an outgoing data stream into a launch data stream based on a respective pre-cursor symbol tap parameter C−M . . . C1−and a symbol tap parameter C0;
ii) supplying the launch data stream to the communication channel;
iii) receiving an incoming data stream from the communication channel;
iv) conditioning the received incoming data stream by passing the incoming data stream through an adaptive linear equalizer and an N Tap Decision Feedback Equalizer (DFE) with corresponding symbol spaced tap parameters [C−M:CN] to produce an equalized serial data stream;
v) sampling the equalized serial data stream to latch user data;
vi) sampling the equalized serial data stream to latch monitor data; and
vii) producing the tap parameters [C−M:CN] from the user data and monitor data;
further including a step of producing gain parameters GDC, GHF and GAGC from the user data and monitor data, and wherein the step of conditioning the received incoming data stream by passing the incoming data stream through an adaptive linear equalizer includes:
i) supplying the incoming data stream to a first signal path through a high-pass filter coupled to a controllable pure gain stage at a gain corresponding to a gain parameter GHF and to a second signal path through a controllable pure gain stage coupled at a gain corresponding to a gain parameter GDC;
ii) summing the outputs of said first and second signal paths; and
iii) supplying the said sum of the outputs to a controllable pure gain stage at a gain corresponding to a gain parameter GAGC to produce the input for said an N Tap Decision Feedback Equalizer (DFE).

### Claim 19 (depends on 18)

The method of claim 18 further including the steps of:
i) over a plurality of symbol periods:
storing the latched user data in a data channel word;
storing the latched monitor data in a monitor channel word; and
ii) producing the symbol spaced tap parameters from selected portions of said stored user data and said stored monitor data.

### Claim 20 (depends on 19)

The method of claim 19 further including the step of generating a bit offset to define a window of data in said data channel word and said monitor channel word whereby the step of producing the symbol spaced tap parameters is based on said data window defining said selected portions of said stored user data and said stored monitor data determined by said bit offset.

### Claim 21 (depends on 20)

The method of claim 20 wherein a pseudo random bit offset is generated each time said symbol spaced tap parameters are produced.