Semiconductor device and offset voltage adjusting method
AssigneeRenesas Electronics Corporation
InventorsJun Fukuhara, Tsuyoshi Mitsuda
Life of this patent
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Abstract
A semiconductor device includes a fuse section having a plurality of fuse circuits configured to generate switch control signals; and an offset adjusting section configured to adjust an offset voltage of a differential amplifier based on the switch control signals supplied from output nodes of the plurality of fuse circuits. Each of the plurality of fuse circuits includes a fuse connected between a first power supply voltage and a cut node; a current source connected between a second power supply voltage and the output node; and a first transistor connected between the output node and the cut node and having a gate connected to the second power supply voltage.
Claims19
A semiconductor device, comprising:
- a fuse section having a plurality of fuse circuits configured to generate switch control signals,
- wherein each of said plurality of fuse circuits comprises:
- a fuse connected between a first power supply voltage and a cut node;
- a current source connected between a second power supply voltage and an output node;
- and
- a first transistor connected between said output node and said cut node and having a gate connected to said second power supply voltage,
- wherein said current source comprises a second transistor whose source and gate are connected with said second power supply voltage, and whose drain is connected with said output node and a drain of said first transistor, and a source of said first transistor is connected with said cut node and said fuse, and
- wherein the second transistor is an N-channel MOS transistor of a depletion type.
A semiconductor device, comprising:
- a fuse section having a plurality of fuse circuits configured to generate switch control signals,
- wherein each of said plurality of fuse circuits comprises:
- a fuse connected between a first power supply voltage and a cut node;
- a current source connected between a second power supply voltage and an output node;
- and
- a first transistor connected between said output node and said cut node and having a gate connected to said second power supply voltage,
- wherein said current source comprises a second transistor whose source and gate are connected with said second power supply voltage, and whose drain is connected with said output node and a drain of said first transistor, and a source of said first transistor is connected with said cut node and said fuse,
- wherein said fuse circuit further comprises:
- a third transistor connected between said output node and said second power supply voltage;
- a fourth transistor connected between said first power supply voltage and the gate of said third transistor, and having a gate connected with the cut node;
- a fifth transistor connected between said second power supply voltage and the gate of said third transistor and having a gate connected with said second power supply voltage;
- a second resistance connected between the gate of said fourth transistor and the cut node;
- and
- a diode connected between the gate of said fourth transistor and said first power supply voltage.
Dependencies are inferred from the claim text.