US 7,940,088 B1Granted

High speed phase frequency detector

AssigneePMC-Sierra, Inc.

InventorsParthasarathy Sampath, Vikas Choudhary

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Abstract

Apparatus and methods detect missing clock edges. An improved phase frequency detector (PFD) can be used in, for example, a phase locked loop (PLL) or a delay locked loop (DLL). Conventional PFDs can miss clock edges. Disclosed is a missing clock edge detection circuit that reliably detects these missing clock edges to correctly activate switches of a charge pump of the PLL or DLL. Embodiments exhibit relatively little of the characteristic polarity reversal of conventional PLL or DLL circuits, which then enables embodiments to operate faster and acquire phase lock quicker than conventional circuits. Such techniques are useful in clock synthesis, clock recovery, and the like. The invention can further include an optional circuit that detects when the missing clock edge detection circuit may have inaccurately determined (false positive) that a clock edge had been missed, to override the corrective action by the missing clock edge detection circuit.

Claims14

Dependent claims

An apparatus comprising:

a phase frequency detector configured to receive a first clock signal and a second clock signal, the phase frequency detector responsive to triggering edges of the first clock signal and the second clock signal, the phase frequency detector configured to generate an up signal and a down signal as control signals for a charge pump of a phase detector, wherein states of the up signal and a state of the down signal are based at least partially on the triggering edges of the first clock signal and the second clock signal, respectively;
a missing clock edge detection circuit configured to determine when a particular triggering edge of the first clock signal or the second clock signal that should generate a response from the phase frequency detector has been missed by the phase frequency detector, and to correct the state of the up signal or the state of the down signal in response to a determination of a missed clock edge;
and
a bypass circuit configured to determine whether a missing clock edge determination by the missing clock edge detection circuit is accurate or not, wherein when the determination is accurate, the bypass circuit is configured to permit the missing clock edge detection circuit to correct the state of the up signal or the state of the down signal, and when the determination is inaccurate, the bypass circuit is configured to inhibit correction by the missing clock edge detection circuit.

1 more element

An apparatus comprising:

a phase frequency detector configured to receive a first clock signal and a second clock signal, the phase frequency detector responsive to triggering edges of the first clock signal and the second clock signal, the phase frequency detector configured to generate an up signal and a down signal as control signals for a charge pump of a phase detector, wherein states of the up signal and a state of the down signal are based at least partially on the triggering edges of the first clock signal and the second clock signal, respectively, wherein the phase frequency detector comprises:
a first flip-flop having a clock input operatively coupled to the first clock signal and having a data input coupled to a first state such that the first flip-flop is configured to latch the up signal to the first state upon occurrence of triggering edges of the first clock signal;
a second flip-flop having a clock input operatively coupled to the second clock signal and having a data input coupled to the first state such that the second flip-flop is configured to latch the down signal to the first state upon occurrence of triggering edges of the second clock signal;
a reset circuit configured to reset the first flip-flop and the second flip-flop to a second state opposite the first state when both the up signal and the down signal are at the first state;
and
a missing clock edge detection circuit configured to determine when a particular triggering edge of the first clock signal or the second clock signal that should generate a response from the phase frequency detector has been missed by the phase frequency detector, and to correct the state of the up signal or the state of the down signal in response to a determination of a missed clock edge, wherein the missing clock edge detection circuit comprises:
a third flip-flop having a clock input operatively coupled to the first clock signal, having a data input operatively coupled to the up signal, wherein the third flip-flop is configured to latch a state of the up signal upon occurrence of triggering edges of the first clock signal to generate an UP_DETECT signal;
a first detection logic circuit configured to set the first flip-flop to the first state when (a) the UP_DETECT signal is at the first state or (b) the up signal is at the second state and the UP_DETECT signal is at the first state at a triggering edge of the first clock signal;
a fourth flip-flop having a clock input operatively coupled to the second clock signal, having a data input operatively coupled to the down signal wherein the fourth flip-flop is configured to latch a state of the down signal upon occurrence of triggering edges of the second clock signal to generate a DN_DETECT signal;
and
a second detection logic circuit configured to set the second flip-flop to the first state when (a) the DN_DETECT signal is at the first state or (b) the down signal is at the second state and the DN_DETECT signal is at the first state at a triggering edge of the second clock signal.

8 more elements

A method for phase detection, the method comprising:

monitoring a phase frequency detector, wherein the phase frequency detector is configured to receive a first clock signal and a second clock signal and to generate an up signal and a down signal for control of a charge pump of a phase detector, wherein states of the up signal and a state of the down signal are based at least partially on triggering edges of the first clock signal and the second clock signal, respectively, wherein the phase frequency detector comprises:
a first flip-flop having a clock input operatively coupled to the first clock signal and having a data input coupled to a first state such that the first flip-flop is configured to latch the up signal to the first state upon occurrence of triggering edges of the first clock signal;
a second flip-flop having a clock input operatively coupled to the second clock signal and having a data input coupled to the first state such that the second flip-flop is configured to latch the down signal to the first state upon occurrence of triggering edges of the second clock signal;
a reset circuit configured to reset the first flip-flop and the second flip-flop to a second state opposite the first state when both the up signal and the down signal are at the first state;
determining when a particular triggering edge of the first clock signal or the second clock signal has been missed by the phase frequency detector;
wherein determining when a particular triggering edge of the first clock signal has been missed comprises determining that (a) an UP_DETECT signal is at the first state or (b) the up signal is at the second state and the UP_DETECT signal is at the first state at a triggering edge of the first clock signal, wherein the UP_DETECT signal is generated by storing a state of the up signal at the triggering edge of the first clock signal;
wherein determining when a particular triggering edge of the second clock signal has been missed comprises determining that (a) a DN_DETECT signal is at the first state or (b) the down signal is at the second state and the DN_DETECT signal is at the first state at a triggering edge of the second clock signal, wherein the DN_DETECT signal is generated by storing a state of the down signal at the triggering edge of the second clock signal;
correcting the state of the up signal or the state of the down signal in response to a determination of a missed clock edge;
wherein correcting the state of the up signal comprises setting the first flip-flop to the first state upon the determination of the missed triggering edge of the first clock signal;
and
wherein correcting the state of the down signal comprises setting the second flip-flop to the first state upon the determination of the missed triggering edge of the second clock signal.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/415,426Filed 31 Mar 2009
Granted: 10 May 2011
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G01R 25/02
Arrangements for measuring phase angle between a voltage and a current or between voltages or currents: in circuits having distributed constants
H03L 7/089
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: the phase or…
H03L 7/1077
Using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth: by changing characteristics of the phase or…
H03D 13/004
In which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means: the logic means…