# US 7,939,856 B2 · Area-efficient distributed device structure for integrated voltage regulators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,939,856 B2 - Document ID: US7939856B2 - Status: Granted - Kind: B2 - Application number: 11/325,236 - Filed: 2006-01-03 - Published: 2006-08-24 - Granted: 2011-05-10 - Earliest claimed: 2004-12-31 - Assignees: STMicroelectronics Pvt. Ltd. - Inventors: Joshipura Jwalant; Nitin Bansal; Amit Katyal; Massimiliano Picca - Web page: https://patentgrep.com/patent/US7939856B2 ## CPC - H05K 3/30: Assembling printed circuits with electric components, e.g. with resistors - G06F 30/36: Circuit design at the analogue level - Y10T 29/49002: Electrical device making - Y10T 29/4913: Assembling to base an electrical component, e.g., capacitor, etc. - Y10T 29/49169: Assembling electrical component directly to terminal or elongated conductor - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract An area efficient distributed device for integrated voltage regulators comprising at least one filler cell connected between a pair of PADS on I/O rail of a chip and at least one additional filler cell having small size replica of said device is coupled to said I/O rails for distributing replicas of said device on the periphery of said chip. The device is connected as small size replica on the lower portion of said second filler cell for distributing said device on the periphery of said chip and providing maximal area utilization. ## Claims ### Claim 1 An area efficient distributed device structure for integrated voltage regulators comprising: at least one filler cell coupled between a pair of pads on an i/o rail of a chip and having a portion of the device structure disposed therein, at least one additional filler cell having a smaller-sized portion of the device structure coupled to the i/o rail for distributing signals of the device structure on a periphery of the chip. ### Claim 2 (depends on 1) An area efficient distributed device structure for integrated voltage regulators as claimed in claim 1, wherein the device structure is a small size replication of a transistor. ### Claim 3 (depends on 2) An area efficient distributed device structure for integrated voltage regulators as claimed in claim 2, wherein the transistor is coupled at an output node of a voltage regulator for driving output current. ### Claim 4 (depends on 1) An area efficient distributed device structure as claimed in claim 1, wherein the at least one additional filler cell comprises multiple sized filler cells corresponding to device layout rules. ### Claim 5 (depends on 1) An area efficient distributed device structure for integrated voltage regulators as claimed in claim 1, wherein the additional filler cell is placed on the i/o rail. ### Claim 6 (depends on 5) An area efficient distributed device structure for integrated voltage regulators as claimed in claim 5, wherein the additional filler cell is coupled around a PAD for distributing the signals corresponding to a size of the device structure. ### Claim 7 An integrated circuit, comprising: a periphery; first and second input-output blocks disposed within the periphery; a first filler cell disposed within the periphery between the first and second input-output blocks; and a voltage regulator having a component disposed within the first input-output block and the first filler cell. ### Claim 8 (depends on 7) The integrated circuit of claim 7, further comprising: an input-supply-voltage rail disposed within the periphery; a regulated-output-voltage rail disposed within the periphery; and wherein the voltage regulator has an input node coupled to the input-supply-voltage rail and has an output node coupled to the regulated-output-voltage rail. ### Claim 9 (depends on 7) The integrated circuit of claim 7 wherein the component comprises a pass transistor. ### Claim 10 (depends on 7) The integrated circuit of claim 7 wherein the component comprises a capacitor. ### Claim 11 (depends on 7) The integrated circuit of claim 7, further comprising: a third input-output block within the periphery; a second filler cell disposed within the periphery between the first and third input-output blocks; and wherein the component is disposed within the second filler cell. ### Claim 12 (depends on 7) The integrated circuit of claim 7, further comprising: third and fourth input-output blocks within the periphery; a second filler cell disposed within the periphery between the third and fourth input-output blocks; and wherein the component is disposed within the second filler cell. ### Claim 13 (depends on 7) The integrated circuit of claim 7, further comprising: an input-supply-voltage rail disposed within the periphery; a regulated-output-voltage rail disposed within the periphery; a control-signal rail disposed within the periphery; and wherein the component comprises a transistor having an input node coupled to the input-supply-voltage rail, an output node coupled to the regulated-output-voltage rail, and a control node coupled to the control-signal rail. ### Claim 14 An integrated circuit, comprising: a periphery; first and second input-output blocks disposed within the periphery and having substantially a same size; a first pad disposed within the periphery and over one of the first and second input-output blocks; and a voltage regulator having a component disposed within the one of the first and second input-output blocks. ### Claim 15 (depends on 14) The integrated circuit of claim 14, further comprising: a filler cell disposed within the periphery; and wherein a first portion of the component is disposed within the one of the first and second input-output blocks and wherein a second portion of the component is disposed within the filler cell. ### Claim 16 (depends on 14) The integrated circuit of claim 14 wherein the component comprises a pass transistor. ### Claim 17 (depends on 14) The integrated circuit of claim 14, further comprising: a second pad disposed within the periphery and being remote from the first and second input-output blocks; a filler cell disposed within the periphery between the first and second pads; and wherein a first portion of the component is disposed within the one of the first and second input-output blocks and wherein a second portion of the component is disposed within the filler cell. ### Claim 18 An electronic system, comprising: an integrated circuit, including a periphery, first and second input-output blocks disposed within the periphery, a first filler cell disposed within the periphery between the first and second input-output blocks, and a voltage regulator having a component disposed within the first input-output block and the first filler cell. ### Claim 19 An electronic system, comprising: an integrated circuit including a periphery, first and second input-output blocks disposed within the periphery and having substantially a same size, a first pad disposed within the periphery and over one of the first and second input-output blocks, and a voltage regulator having a component disposed within the one of the first and second input-output blocks.