Three-dimensional silicon on oxide device isolation
AssigneeInternational Business Machines Corporation
InventorLevent Gulari
Life of this patent
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Abstract
A silicon-on-insulator wafer (10). The SOI wafer (10) comprises a top silicon layer (6), a silicon substrate (4), and an oxide insulator layer (2) disposed across the wafer (10) and between the silicon substrate (4) and the top silicon layer (6). The oxide insulator layer (2) has at least one of a contoured top surface (8a, 8b, 8c, 8d, 8e) and a contoured bottom surface (12e). Also provided are processes for manufacturing such a SOI wafer (10).
Claims13
A process for manufacturing a silicon-on-insulator wafer comprising the steps of:
- providing a silicon substrate;
- forming an oxide insulator layer across the wafer by oxygen implantation, the insulator layer being buried within the silicon substrate, dividing the silicon substrate from a top silicon layer, and having a top surface and a bottom surface;
- thickening the insulator layer by reducing one or more of the implantation dose, energy, and temperature;
- creating at least one of a contoured top surface and a contoured bottom surface of the insulator layer by adjusting one or more of the implantation dose, energy, and temperature;
- and
- annealing to further thicken and contour the insulator layer.
A process for manufacturing a silicon-on-insulator wafer comprising the steps of:
- providing a silicon substrate;
- forming an oxide insulator layer across the wafer by oxygen implantation, the insulator layer being buried within the silicon substrate, dividing the silicon substrate from a top silicon layer, and having a top surface and a bottom surface;
- thickening the insulator layer by reducing one or more of the implantation dose, energy, and temperature;
- generating the chip periodicity for the wafer and setting the coordinates where a predetermined topography of the buried oxide insulator layer is desired;
- transferring the coordinates to an oxygen implanter for implementation;
- adjusting the energy, dose, or temperature of the oxygen implant with the implanter scanning and the wafer tilting or rotating according to preset coordinates from the chip periodicity map at the predetermined thicknesses and contours required, thereby creating at least one of a contoured top surface and a contoured bottom surface of the insulator layer;
- and
- annealing to further thicken and contour the insulator layer.
Dependencies are inferred from the claim text.