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US 7,935,603 B1Granted
Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
AssigneesHRL Laboratories, LLC, Raytheon Company, Promtek
InventorsLap-Wai Chow, William M. Clark, Jr., Gavin J. Harbison, Paul Ou Yang
Life of this patent
Estimating the term…
Abstract
A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.
Claims15
A method of camouflaging a circuit, comprising:
- forming a gate structure in a substrate;
- forming a first active region in the substrate;
- providing a first lightly doped density active region adjacent the first active region, said first lightly doped density active region having a first conductivity type and said adjacent first active region having a second conductivity type;
- forming a second active region in the substrate;
- forming a second lightly doped density active region adjacent the second active region, said second lightly doped density active region having a first conductivity type and said adjacent second active region having a second conductivity type;
- forming a conductive layer disposed over at least a portion of said first active regions;
- and
- forming a gap in the conductive layer such that the gap prevents an electrical path from the conductive layer to the first lightly doped density active region for a nominal voltage applied to the conductive layer;
- wherein the circuit is non-operational when the nominal voltage is applied.
6 more elements
A method for camouflaging a circuit, comprising:
- providing a substrate;
- forming source and drain structures in said substrate on either side of a gate structure, the source and drain structures being of a first conductivity type:
- forming a first lightly doped region in said substrate disposed in contact with said source structure and adjacent said gate structure, said first lightly doped region being of a second conductivity type;
- forming a second lightly doped region in said substrate disposed in contact with said drain structure, said second lightly doped region being of the second conductivity type;
- forming a first conductive layer disposed over and in contact with at least a portion of said source region;
- and
- forming a second conductive layer disposed over and in contact with at least a portion of said drain region;
- the first and second conductive layers having a mask selectable width for controlling whether said first and second conductive layers make contact with said first and said second lightly doped regions to thereby selectively control whether the circuit is permanently ON or permanently OFF.
5 more elements
A method of camouflaging a circuit, comprising:
- forming a gate structure in a substrate;
- forming a first active region in the substrate;
- providing a first lightly doped density active region adjacent the first active region, said first lightly doped density active region having a first conductivity type and said adjacent first active region having a second conductivity type;
- forming a second active region in the substrate;
- forming a second lightly doped density active region adjacent the second active region, said second lightly doped density active region having a first conductivity type and said adjacent second active region having a second conductivity type;
- and
- forming a conductive layer disposed over said first active region and said first lightly doped density active region such that said conductive layer provides an electrical path for a nominal voltage from said conductive layer to the first lightly doped density active region;
- wherein the circuit is non-operational when the nominal voltage is applied to said conductive layer.
5 more elements
Dependencies are inferred from the claim text.