Techniques for reducing a voltage swing

A method for reducing a voltage swing comprising the steps of:

• arranging a plurality of dynamic random access memory cells in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors having:
• a first region coupled to a source line;
• a second region coupled to a bit line;
• a first body region disposed between the first region and the second region, wherein the first body region is electrically floating and charged to a first predetermined voltage potential;
• and
• a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region;
• and
• supplying a first voltage and a second voltage to the source line, wherein a difference between the first voltage and the second voltage is less than 3.5V.

An article of manufacture for reducing a voltage swing, the article of manufacture comprising:

• at least one processor readable medium;
• and
• instructions carried on the at least one medium;
• wherein the instructions are configured to be readable from the at least one medium by at least one processor and thereby cause the at least one processor to operate so as to:
• arranging a plurality of dynamic random access memory cells in arrays of rows and columns, each dynamic random access memory cell including one or more memory transistors having:
• a first region coupled to a source line;
• a second region coupled to a bit line;
• a first body region disposed between the first region and the second region, wherein the first body region is electrically floating and charged to a first predetermined voltage potential;
• and
• a first gate coupled to a word line spaced apart from, and capacitively coupled to, the first body region;
• and
• supplying a first voltage and a second voltage to the source line, wherein difference between the first voltage and the second voltage is less than 3.5V.