System and software for performing matrix multiply extract operations
AssigneeMicroUnity Systems Engineering, Inc.
InventorsCraig Hansen, John Moussouris, Alexia Massalin
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicroUnity Systems Engineering, Inc.
InventorsCraig Hansen, John Moussouris, Alexia Massalin
Estimating the term…
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.
A data processing system comprising:
An article of manufacture for use with a processor including a first data path having a first bit width, a second data path having a second bit width greater than the first bit width, a plurality of third data paths having a combined bit width less than the second bit width, a wide operand storage coupled to the first data path and the second data path for storing a wide operand received over the first data path, the wide operand having a size with a number of bits greater than the first bit width, a register file including registers having the first bit width, the register file being connected to the third data paths, and including a wide operand register storing a wide operand specifier that specifies an address of the wide operand, the article of manufacture comprising a non-transitory computer readable medium having computer readable code therein for causing a processor to execute a single matrix-multiply-extract instruction containing instruction fields specifying the wide operand register, a vector operand register in the register file, a control register in the register file, and a results register in the register file, wherein the following operations are performed in response to the single instruction:
Dependencies are inferred from the claim text.