Processor capable of reconfiguring a logical circuit

A processor that executes a program including a plurality of instructions, comprising:

• a reconfigurable integrated circuit;
• a reconfiguration unit operable to reconfigure a part of the reconfigurable integrated circuit based on a circuit configuration information set;
• a configuration information storing unit that stores therein circuit configuration information sets corresponding one-to-one to the instructions;
• a selection unit operable to select two or more instructions for all of which the reconfigurable integrated circuit is reconfigurable at the same time based on the circuit configuration information sets;
• and
• an execution unit operable to execute the two or more instructions in parallel using the reconfigurable integrated circuit that has been reconfigured based on configuration information sets respectively corresponding to the two or more instructions, wherein while the given instructions are being executed, the execution unit has the reconfiguration unit reconfigure the reconfigurable integrated circuit in part using an area where it is not currently used for execution of the two of more instructions, based on the circuit configuration information set corresponding to the instruction selected in the selection unit.

A thread execution method used by a processor that includes a reconfigurable integrated circuit and cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising:

• a reconfiguration step of reconfiguring a part of the reconfigurable integrated circuit based on a circuit configuration information set;
• a configuration information storing step of storing, in a memory, circuit configuration information sets corresponding one-to-one to the threads;
• a control step of putting each thread into execution using the reconfigurable integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread;
• and
• a selection step of selecting, while a given thread put into execution in the control step is being executed, a thread to be executed next, based on an amount of an area in the reconfigurable integrated circuit other than an area used by the given thread an amount of an area in the reconfigurable integrated circuit required for reconfiguring the reconfigurable integrated circuit based on the circuit configuration information sets, wherein
• while the given thread is being executed, the control step has the reconfiguration step reconfigure the reconfigurable integrated circuit in part using an area where it is not currently used for execution of the given thread, based on the circuit configuration information set corresponding to the thread selected at the selection step.

A processor comprising:

• an instruction fetch unit operable to fetch an instruction code including an operation code and an operand from an instruction storage;
• an instruction decode unit operable to decode the instruction code;
• an instruction execution unit including a reconfigurable computing device;
• a control unit operable to control the instruction execution unit according to a result of decoding by the instruction decode unit;
• and
• a configuration information storing unit storing, for each of a plurality of operation codes, a circuit configuration information set used for configuration of a circuit required for execution of processing indicated by the operation code, the plurality of operation codes classified according to operand types thereof, wherein
• the instruction decode unit gives the reconfigurable computing device an instruction to perform reconfiguration of the reconfigurable computing device according to a result of decoding by the instruction decode unit,
• the reconfigurable computing device performs the reconfiguration according to the instruction by using a circuit configuration information set corresponding to an operation code obtained through the decoding by the instruction decode unit, and
• the control unit issues an instruction code decoded by the instruction decode unit to the reconfigurable computing device that has completed the reconfiguration, thereby controlling the instruction execution unit to execute, on data indicated by an operand included in the instruction code, processing indicated by the operation code, wherein while the given operation code is being executed, a selection unit selects an operation code to be executed next, based on an amount of an area in the circuit other than an area being used by the given operation code and an amount of an area in the circuit required for reconfiguring the circuit based on the circuit configuration information sets, and the control unit has the reconfigurable computing device reconfigure the circuit in part using an area that is not currently used for execution of processing indicated by the operation code, based on the circuit configuration information set corresponding to operation code selected in the selection unit.