Compiler method for extracting and accelerator template program

A compilation method for extracting and implementing an accelerator control program from an application source code in a processor based system consisting of an accelerator, one or more processors and one or more main memories, wherein the accelerator comprise direct memory accesses, compute cores, local memories and a programmable accelerator controller unit and the application source code comprises arrays and loops, said compilation method comprising the steps of:

• performing loop nest analysis, wherein said loop nest analysis consists of dependence analysis and pointer analysis and wherein dependence analysis determines the conflicts between the various references to arrays in the loop and pointer analysis determines if two pointer references in a loop are in conflict;
• performing transformations to convert the loops from their original sequential execution semantics to parallel execution semantics, wherein said step of performing transformations further comprises the steps of:
• conducting loop tiling, wherein loop tiling is a compiler transformation that divides the iterations of the loop nest into tiles and the size of the tile is selected based on the amount of local memory available and on the required performance of the accelerator;
• and
• conducting input compute output loop creation, wherein the inner-most loop created by the loop tiling process is split into multiple loops and classifying each of the split loops into an inner input, compute or output activity of the accelerator;
• performing back-end processes for creating an accelerator control program that parallelizes the activities of the components of the accelerator, using the output of the loop-nest analysis and transformation, further comprising the steps of:
• determining the parameters of the accelerator including the number of direct memory access channels, size and number of random access memory banks and the connectivity between the ports of the random access memory banks and the compute core;
• determining the memory map containing said accelerator's address space, the address location of the accelerator's components, and the address of the accelerator local variable;
• generating the accelerator control program comprising a sequential control program;
• wherein generating the sequential control program comprises the steps of:
• processing each inner input, compute or output loop;
• generating the controller program in the same sequence as the inner loops of the transformed loop;
• converting each statement of an input loop into a direct memory access command that reads from main memory into a random access memory bank;
• converting each statement of an output loop into a direct memory access command that writes from a random access memory bank into global memory;
• converting each compute loop into a command to initiate the compute core;
• inserting a wait statement after each DMA or compute core command;
• converting the outer loop into a loop statement of the accelerator controller program that encloses all the direct memory access and compute core statements;
• and,
• converting a outer nest, if present, into a loop statement enclosing all other statements,
• generating hardware dependent software, wherein the hardware dependent software is a software layer that provides interfaces to allow the application software to interact with the accelerator hardware;
• and,
• modifying the application source code in order to invoke the hardware dependent software for executing the accelerator control program.