Common clock path pessimism analysis for circuit designs using clock tree networks

A method to perform timing analysis of a design containing clock networks, the method comprising:

• transforming a clock network into a clock tree;
• populating the clock tree with information regarding source and destination registers in the design;
• enumerating a Common Clock Path Pessimism (CCPP) groups, wherein any source register and any destination register in a CCPP group have a same nearest common ancestor node in the clock tree;
• eliminating CCPP using the enumerated CCPP groups;
• outputting the timing analysis results;
• and
• performing the timing analysis for rising arrival clock times and falling arrival clock times and for different combinations of rising source registers, rising destination registers, falling source registers, and falling destination registers, wherein each operation of the method is executed by a processor.

A computer program embedded in a non-transitory computer-readable storage medium, when executed by one or more processors, for performing timing analysis of designs containing clock networks by incorporating Common Clock Path Pessimism, the computer program comprising:

• computer code for transforming a clock network into a clock tree;
• computer code for populating the clock tree with information regarding source and destination registers in the design;
• computer code for enumerating a CCPP group for nodes in the clock tree, the CCPP group of any of the nodes including all source registers that are direct children of the node and all destination registers that are descendants of the node in the clock tree, wherein any source register and any destination register in a CCPP group have a same nearest common ancestor node in the clock tree;
• computer code for eliminating CCPP using the enumerated CCPP groups;
• and
• computer code for outputting the timing analysis results.

A system to perform timing analysis of designs containing clock networks by incorporating Common Clock Path Pessimism, the system comprising:

• a computer device having a processor;
• a display to show results of the timing analysis;
• and
• a memory, the memory including,
• a model of the design, and
• a timing analysis program,
• wherein the program instructions from the timing analysis program when executed by the processor cause the processor to,
• transform a clock network into a clock tree;
• populate the clock tree with information regarding source and destination registers in the design;
• enumerate a CCPP group for nodes in the clock tree, the CCPP group of any of the nodes including all source registers that are direct children of the node and all destination registers that are descendants of the node in the clock tree, wherein any source register and any destination register in a CCPP group have a same nearest common ancestor node in the clock tree;
• eliminate CCPP using the enumerated CCPP groups;
• and
• output the timing analysis results.