Method and apparatus for generating a layout for a transistor
AssigneeSynopsys, Inc.
InventorsVictor Moroz, Xi-Wei Lin, Mark Rubin
Life of this patent
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Abstract
A system that generates a layout for a transistor is presented. During operation, the system receives a transistor library which includes operating characteristics of fabricated transistors correlated to transistor gate shapes. The system also receives one or more desired operating characteristics for the transistor. Next, the system determines a transistor gate shape for the transistor based on the transistor library so that a fabricated transistor with the transistor gate shape substantially achieves the one or more desired operating characteristics. The system then generates the layout for the transistor which includes the transistor gate shape.
Claims19
A method for generating a physical layout for a transistor, comprising:
- determining a transistor gate shape for the transistor based on a transistor library so that a fabricated transistor with the transistor gate shape substantially achieves one or more desired operating characteristics, wherein the transistor library includes a correlation between operating characteristics of fabricated transistors and transistor gate shapes;
- and
- generating, by computer, the physical layout for the transistor, wherein the physical layout includes the transistor gate shape, and wherein the physical layout is used to fabricate the transistor.
A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for generating a physical layout for a transistor, wherein the method comprises:
- determining a transistor gate shape for the transistor based on a transistor library so that a fabricated transistor with the transistor gate shape substantially achieves one or more desired operating characteristics, wherein the transistor library includes a correlation between operating characteristics of fabricated transistors and transistor gate shapes;
- and
- generating the physical layout for the transistor, wherein the physical layout includes the transistor gate shape, and wherein the physical layout is used to fabricate the transistor.
An apparatus that generates a physical layout for a transistor, comprising:
- an analysis mechanism configured to determine a transistor gate shape for the transistor based on a transistor library so that a fabricated transistor with the transistor gate shape substantially achieves one or more desired operating characteristics, wherein the transistor library includes a correlation between operating characteristics of fabricated transistors and transistor gate shapes;
- and
- a layout-generation mechanism configured to generate the physical layout for the transistor, wherein the physical layout includes the transistor gate shape, and wherein the physical layout is used to fabricate the transistor.
Dependencies are inferred from the claim text.