Timing driven logic block configuration
AssigneeXilinx, Inc.
InventorsPriya Sundararajan, Sridhar Krishnamurthy
Life of this patent
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Abstract
A method of configuring a logic block of a programmable logic device (PLD) during physical implementation of a circuit design, wherein ports of the logic block are selectively registered, can include identifying the logic block of the PLD, wherein the logic block is located on a critical path. For each of a plurality of selectively registerable portions of the logic block, the method can include computing input slacks and output slacks based upon potential register usage within the logic block. The method further can include determining register usage for the logic block by maximizing a function which depends upon a measure of worst case slack for pipeline stages.
Claims18
A method of configuring a logic block of an integrated circuit during physical implementation of a circuit design, said method comprising:
- measuring slack for a port of the logic block, wherein the port is selectively registered, wherein the logic block comprises dedicated circuitry that performs a particular function, and wherein the logic block comprises at least one register that is selectively bypassed to facilitate selective registering of the port;
- identifying a first location of a register associated with the port as internal, wherein the register is implemented as the at least one register that is selectively bypassed, or external with respect to the logic block, wherein the register is implemented within fabric of the integrated circuit and the at least one register of the port is bypassed;
- moving, via a computer, the register associated with the port to a second location according to a relocation technique, wherein the second location is internal or external with respect to the logic block and different than the first location;
- determining whether slack for the port improves when the register associated with the port is moved to the second location as compared to the first location;
- and
- if the slack for the port improves when the register associated with the port is moved to the second location, accepting the second location of the register.
A non-transitory computer-readable medium having computer-executable instructions for performing a method comprising:
- measuring slack for a port of a logic block of an integrated circuit, wherein the port is selectively registered, wherein the logic block comprises dedicated circuitry that performs a particular function, and wherein the logic block comprises at least one register that is selectively bypassed to facilitate selective registering of the port;
- identifying a first location of a register associated with the port as internal, wherein the register is implemented as the at least one register that is selectively bypassed, or external with respect to the logic block, wherein the register is implemented within fabric of the integrated circuit and the at least one register of the port is bypassed;
- moving the register associated with the port to a second location according to a relocation technique, wherein the second location is internal or external with respect to the logic block and different than the first location;
- determining whether slack for the port improves when the register associated with the port is moved to the second location as compared to the first location;
- and
- if the slack for the port improves when the register associated with the port is moved to the second location, accepting the second location of the register.
A system comprising:
- a computer programmed to configure a logic block of an integrated circuit during physical implementation of a circuit design, wherein the computer is programmed to perform steps comprising:
- measuring slack for a port of the logic block, wherein the port is selectively registered, wherein the logic block comprises dedicated circuitry that performs a particular function, and wherein the logic block comprises at least one register that is selectively bypassed to facilitate selective registering of the port;
- identifying a first location of a register associated with the port as internal, wherein the register is implemented as the at least one register that is selectively bypassed, or external with respect to the logic block, wherein the register is implemented within fabric of the integrated circuit and the at least one register of the port is bypassed;
- moving, via a computer, the register associated with the port to a second location according to a relocation technique, wherein the second location is internal or external with respect to the logic block and different than the first location;
- determining whether slack for the port improves when the register associated with the port is moved to the second location as compared to the first location;
- and
- if the slack for the port improves when the register associated with the port is moved to the second location, accepting the second location of the register.
Dependencies are inferred from the claim text.