Optimization method for fractional-N phased-lock-loop (PLL) system
AssigneeInternational Business Machines Corporation
InventorKai Di Feng
Life of this patent
Estimating the term…
Abstract
In one general embodiment, a method is provided. In operation, a first phase noise in a first circuit located on an integrated circuit is determined. Additionally, a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit is determined, the second circuit being programmable. Furthermore, the first phase noise is compared with the second phase noise. Also, the second circuit is conditionally modified to optimize the performance of the integrated circuit, based on a result of the comparison. Additional methods are also presented.
Claims20
A method, comprising:
- determining a first phase noise in a first circuit located on an integrated circuit;
- determining a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit, the second circuit being programmable;
- comparing, using a circuit or computing device, the first phase noise with the second phase noise;
- and
- conditionally modifying the second circuit to optimize a performance of the integrated circuit, based on a result of the comparison.
A method, comprising:
- determining a first phase noise in a first circuit located on an integrated circuit;
- determining a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit, the second circuit being programmable;
- comparing, using a circuit or computing device, the first phase noise with the second phase noise;
- conditionally modifying the second circuit to optimize a performance of the integrated circuit, based on a result of the comparison;
- wherein the first circuit includes:
- a voltage controlled oscillator for generating a periodic output signal;
- a phase detector for controlling the voltage controlled oscillator;
- a charge pump for modifying an input to the voltage controlled oscillator;
- a frequency divider in a feedback path for modifying a frequency of the output signal;
- a first multiplexer;
- and
- a first random number generator;
- and
- wherein the second circuit includes:
- a second multiplexer;
- and
- a second random number generator.
A method, comprising:
- determining a first phase noise in a first circuit located on an integrated circuit;
- determining a second phase noise in a second circuit coupled to the first circuit but which is not located in the integrated circuit, the second circuit being programmable;
- comparing, using a circuit or computing device, the first phase noise with the second phase noise;
- conditionally modifying the second circuit to optimize a performance of the integrated circuit, based on a result of the comparison;
- and
- conditionally modifying the first circuit to optimize the performance of the integrated circuit, based on a result of the comparison.
Dependencies are inferred from the claim text.